公开(公告)号：US07745338B2

公开(公告)日：2010-06-29

申请号：US11738155

申请日：2007-04-20

申请人： Ji-hoon Cha ,  Chang-ki Hong ,  Kun-tack Lee ,  Woo-gwan Shim ,  Chang-sup Mun ,  Ho-wook Choi

发明人： Ji-hoon Cha ,  Chang-ki Hong ,  Kun-tack Lee ,  Woo-gwan Shim ,  Chang-sup Mun ,  Ho-wook Choi

IPC分类号： H01L21/311 ,  H01L21/76 ,  H01L21/4763

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/32139

摘要： A method of forming fine pitch hardmask patterns includes forming a hardmask layer on a substrate and forming a plurality of first mask patterns on the hardmask layer. A buffer layer is formed on the plurality of first mask patterns, and has an upper surface defining recesses between adjacent first mask patterns. Second mask patterns are formed within the recesses formed in the upper surface of the buffer layer. The buffer layer is partially removed to expose upper surfaces of the plurality of first mask patterns, and the buffer layer is then partially removed using the first mask patterns and the second mask patterns as an etch mask to expose the hardmask layer between the first mask pattern and the second mask pattern. Using the first mask patterns and the second mask patterns as an etch mask, the hardmask layer is etched to form hardmask patterns.

摘要翻译： 形成细间距硬掩模图案的方法包括在基底上形成硬掩模层并在硬掩模层上形成多个第一掩模图案。 缓冲层形成在多个第一掩模图案上，并且具有在相邻的第一掩模图案之间限定凹部的上表面。 在形成在缓冲层的上表面中的凹部内形成第二掩模图案。 部分地去除缓冲层以暴露多个第一掩模图案的上表面，然后使用第一掩模图案和第二掩模图案作为蚀刻掩模来部分地去除缓冲层，以在第一掩模图案之间暴露硬掩模层 和第二掩模图案。 使用第一掩模图案和第二掩模图案作为蚀刻掩模，硬掩模层被蚀刻以形成硬掩模图案。

公开(公告)号：US20080014752A1

公开(公告)日：2008-01-17

申请号：US11738155

申请日：2007-04-20

申请人： Ji-hoon Cha ,  Chang-ki Hong ,  Kun-tack Lee ,  Woo-gwan Shim ,  Chang-sup Mun ,  Ho-wook Choi

发明人： Ji-hoon Cha ,  Chang-ki Hong ,  Kun-tack Lee ,  Woo-gwan Shim ,  Chang-sup Mun ,  Ho-wook Choi

IPC分类号： H01L21/311

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/32139

摘要： A method of forming fine pitch hardmask patterns includes forming a hardmask layer on a substrate and forming a plurality of first mask patterns on the hardmask layer. A buffer layer is formed on the plurality of first mask patterns, and has an upper surface defining recesses between adjacent first mask patterns. Second mask patterns are formed within the recesses formed in the upper surface of the buffer layer. The buffer layer is partially removed to expose upper surfaces of the plurality of first mask patterns, and the buffer layer is then partially removed using the first mask patterns and the second mask patterns as an etch mask to expose the hardmask layer between the first mask pattern and the second mask pattern. Using the first mask patterns and the second mask patterns as an etch mask, the hardmask layer is etched to form hardmask patterns.

摘要翻译： 形成细间距硬掩模图案的方法包括在基底上形成硬掩模层并在硬掩模层上形成多个第一掩模图案。 缓冲层形成在多个第一掩模图案上，并且具有在相邻的第一掩模图案之间限定凹部的上表面。 在形成在缓冲层的上表面中的凹部内形成第二掩模图案。 部分地去除缓冲层以暴露多个第一掩模图案的上表面，然后使用第一掩模图案和第二掩模图案作为蚀刻掩模来部分地去除缓冲层，以在第一掩模图案之间暴露硬掩模层 和第二掩模图案。 使用第一掩模图案和第二掩模图案作为蚀刻掩模，硬掩模层被蚀刻以形成硬掩模图案。

公开(公告)号：US20070082471A1

公开(公告)日：2007-04-12

申请号：US11546420

申请日：2006-10-12

申请人： Dae-hyuk Kang ,  Jung-min Oh ,  Chang-ki Hong ,  Sang-jun Choi ,  Woo-gwan Shim

发明人： Dae-hyuk Kang ,  Jung-min Oh ,  Chang-ki Hong ,  Sang-jun Choi ,  Woo-gwan Shim

IPC分类号： H01L21/3205

CPC分类号： H01L28/90 ,  H01L21/0334 ,  H01L21/31144 ,  H01L27/10852

摘要： In one aspect, a method of fabricating a semiconductor memory device is provided which includes forming a mold insulating film over first and second portions of a semiconductor substrate, where the mold insulating film includes a plurality of storage node electrode holes spaced apart over the first portion of the semiconductor substrate. The method further includes forming a plurality of storage node electrodes on inner surfaces of the storage node electrode holes, respectively, and forming a capping film which covers the storage node electrodes and a first portion of the mold insulating film located over the first portion of the semiconductor substrate, and which exposes a second portion of the mold insulating film located over the second portion of the semiconductor substrate. The method further includes selectively removing, including wet etching, the mold insulating film to expose a sidewall of at least one storage node electrode among the storage node electrodes covered by the capping film, and removing the capping film by dry etching to expose upper portions of the storage node electrodes.

摘要翻译： 一方面，提供一种制造半导体存储器件的方法，其包括在半导体衬底的第一和第二部分上形成模绝缘膜，其中所述模绝缘膜包括在所述第一部分上分开的多个存储节点电极孔 的半导体衬底。 该方法还包括分别在存储节点电极孔的内表面上形成多个存储节点电极，并且形成覆盖存储节点电极的封盖膜和位于第一部分上的模具绝缘膜的第一部分 半导体衬底，并且暴露位于半导体衬底的第二部分上方的模具绝缘膜的第二部分。 该方法还包括选择性地去除包括湿式蚀刻的模具绝缘膜，以暴露由覆盖膜覆盖的存储节点电极中的至少一个存储节点电极的侧壁，以及通过干蚀刻去除封盖膜以暴露 存储节点电极。

公开(公告)号：US20060246666A1

公开(公告)日：2006-11-02

申请号：US11410837

申请日：2006-04-26

申请人： Jeong-nam Han ,  Dong-chan Kim ,  Chang-jin Kang ,  Kyeong-koo Chi ,  Woo-gwan Shim ,  Hyo-san Lee ,  Chang-ki Hong ,  Sang-jun Choi

发明人： Jeong-nam Han ,  Dong-chan Kim ,  Chang-jin Kang ,  Kyeong-koo Chi ,  Woo-gwan Shim ,  Hyo-san Lee ,  Chang-ki Hong ,  Sang-jun Choi

IPC分类号： H01L21/336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11543

摘要： A method of fabricating a flash memory having a U-shape floating gate is provided. The method includes forming adjacent isolation layers separated by a gap and forming a tunnel oxide layer in the gap. After a conductive layer is formed on the tunnel oxide layer to a thickness not to fill the gap, a polishing sacrificial layer is formed on the conductive layer. The sacrificial layer and the conductive layer on the isolation layers are removed, thereby forming a U-shape floating gate self-aligned in the gap, and concurrently forming a sacrificial layer pattern within an inner portion of the floating gate. Selected isolation layers are then recessed to expose sidewalls of the floating gate. The sacrificial layer pattern is then removed from the floating gate to expose an upper surface of the floating gate.

摘要翻译： 提供一种制造具有U形浮动栅极的闪速存储器的方法。 该方法包括形成由间隙隔开并在间隙中形成隧道氧化物层的相邻隔离层。 在隧道氧化物层上形成导电层至不填充间隙的厚度之后，在导电层上形成抛光牺牲层。 除去隔离层上的牺牲层和导电层，从而在间隙中形成自对准的U形浮动栅极，同时在浮栅的内部部分内形成牺牲层图案。 然后将选定的隔离层凹入以露出浮动栅极的侧壁。 然后从浮动栅极去除牺牲层图案以暴露浮动栅极的上表面。

公开(公告)号：US07459370B2

公开(公告)日：2008-12-02

申请号：US11546420

申请日：2006-10-12

申请人： Dae-hyuk Kang ,  Jung-min Oh ,  Chang-ki Hong ,  Sang-jun Choi ,  Woo-gwan Shim

发明人： Dae-hyuk Kang ,  Jung-min Oh ,  Chang-ki Hong ,  Sang-jun Choi ,  Woo-gwan Shim

IPC分类号： H01L21/20

CPC分类号： H01L28/90 ,  H01L21/0334 ,  H01L21/31144 ,  H01L27/10852

摘要： In one aspect, a method of fabricating a semiconductor memory device is provided which includes forming a mold insulating film over first and second portions of a semiconductor substrate, where the mold insulating film includes a plurality of storage node electrode holes spaced apart over the first portion of the semiconductor substrate. The method further includes forming a plurality of storage node electrodes on inner surfaces of the storage node electrode holes, respectively, and forming a capping film which covers the storage node electrodes and a first portion of the mold insulating film located over the first portion of the semiconductor substrate, and which exposes a second portion of the mold insulating film located over the second portion of the semiconductor substrate. The method further includes selectively removing, including wet etching, the mold insulating film to expose a sidewall of at least one storage node electrode among the storage node electrodes covered by the capping film, and removing the capping film by dry etching to expose upper portions of the storage node electrodes.

摘要翻译： 一方面，提供一种制造半导体存储器件的方法，其包括在半导体衬底的第一和第二部分上形成模绝缘膜，其中所述模绝缘膜包括在所述第一部分上分开的多个存储节点电极孔 的半导体衬底。 该方法还包括分别在存储节点电极孔的内表面上形成多个存储节点电极，并且形成覆盖存储节点电极的封盖膜和位于第一部分上的模具绝缘膜的第一部分 半导体衬底，并且暴露位于半导体衬底的第二部分上方的模具绝缘膜的第二部分。 该方法还包括选择性地去除包括湿式蚀刻的模具绝缘膜，以暴露由覆盖膜覆盖的存储节点电极中的至少一个存储节点电极的侧壁，以及通过干蚀刻去除封盖膜以暴露 存储节点电极。

公开(公告)号：US20070051700A1

公开(公告)日：2007-03-08

申请号：US11444416

申请日：2006-06-01

申请人： Hyo-san Lee ,  Sang-yong Kim ,  Chang-ki Hong ,  Woo-gwan Shim ,  Jeong-nam Han

发明人： Hyo-san Lee ,  Sang-yong Kim ,  Chang-ki Hong ,  Woo-gwan Shim ,  Jeong-nam Han

IPC分类号： C23F1/00 ,  B44C1/22 ,  C09K13/00

CPC分类号： H01L21/02071 ,  C11D3/042 ,  C11D3/046 ,  C11D3/2075 ,  C11D11/0047 ,  H01L21/0206 ,  H01L29/40117

摘要： Provided are a substrate cleaning composition including a fluoride compound, an inorganic acid, and deionized water, and a method of forming a gate using the same. The fluoride compound is one of HF, NH4F, and a combination thereof, and the inorganic acid is one of HNO3, HCI, HCIO4, H2SO4, or H5IO6. The substrate cleaning composition removes polymer by-products generated by etching a metal layer for forming a gate, but not other layers.

摘要翻译： 提供了包含氟化物，无机酸和去离子水的基板清洗组合物，以及使用其形成栅极的方法。 氟化合物是HF，NH 4 F及其组合中的一种，无机酸是HNO 3，HCl，HCIO 4， H 2 SO 2，或H 5 O 6 6，或H 5 O 6。 基板清洁组合物除去通过蚀刻用于形成栅极的金属层而不是其它层而产生的聚合物副产物。

公开(公告)号：US20060228890A1

公开(公告)日：2006-10-12

申请号：US11402028

申请日：2006-04-12

申请人： Hyo-san Lee ,  Sang-yong Kim ,  Chang-ki Hong ,  Sang-jun Choi ,  Woo-gwan Shim ,  Im-soo Park ,  Kui-jong Baik ,  Woong Han ,  Jung-hun Lim ,  Sang-won Lee ,  Sung-bae Kim ,  Hyun-tak Kim

发明人： Hyo-san Lee ,  Sang-yong Kim ,  Chang-ki Hong ,  Sang-jun Choi ,  Woo-gwan Shim ,  Im-soo Park ,  Kui-jong Baik ,  Woong Han ,  Jung-hun Lim ,  Sang-won Lee ,  Sung-bae Kim ,  Hyun-tak Kim

IPC分类号： C03C15/00 ,  H01L21/302 ,  B08B6/00 ,  C09K13/00

CPC分类号： H01L21/0206 ,  C09K13/08 ,  C23G1/10 ,  H01L21/02071

摘要： A cleaning solution includes acetic acid, an inorganic acid, a fluoride compound, and deionized water, and may further include a corrosion inhibitor, a chelating agent, or a combination thereof. The cleaning solution may be used in the formation of a metal pattern in which a metal film including ruthenium is formed on a surface of a substrate, and a portion of the metal film is dry-etched to form a metal film pattern. After dry-etching, the metal film pattern is cleaned with the cleaning solution to remove an etching by-product layer around the metal film pattern. The cleaning solution may also be used to remove an etching by-product layer around an oxide film pattern prior to dry-etching of the metal film.

摘要翻译： 清洁溶液包括乙酸，无机酸，氟化物和去离子水，并且还可以包括腐蚀抑制剂，螯合剂或其组合。 清洗液可用于形成在基材表面上形成包含钌的金属膜的金属图案，并且将金属膜的一部分干蚀刻以形成金属膜图案。 在干蚀刻之后，用清洁溶液清洗金属膜图案以除去金属膜图案周围的蚀刻副产物层。 在干蚀刻金属膜之前，还可以使用清洁溶液去除氧化膜图案周围的蚀刻副产物层。

公开(公告)号：US20070218619A1

公开(公告)日：2007-09-20

申请号：US11714850

申请日：2007-03-07

申请人： Ji-hoon Cha ,  Woo-gwam Shim ,  Dong-gyun Han ,  Chang-ki Hong ,  Seung-pil Chung

发明人： Ji-hoon Cha ,  Woo-gwam Shim ,  Dong-gyun Han ,  Chang-ki Hong ,  Seung-pil Chung

IPC分类号： H01L21/8238

CPC分类号： H01L21/76224 ,  Y10S438/954

摘要： A method of manufacturing a nonvolatile semiconductor memory device may include forming a pad oxide layer pattern and a mask pattern on a semiconductor substrate, forming a trench within the semiconductor substrate with the mask pattern functioning as an etching mask, sequentially forming a first device isolation layer and a second device isolation layer that may fill the trench, forming an opening by removing the mask pattern to expose an upper surface of the pad oxide layer pattern and a sidewall of the second device isolation layer, and forming a floating gate forming region having a width wider than the opening by simultaneously removing the pad oxide layer pattern and a sidewall portion of the second device isolation layer exposed by the opening.

摘要翻译： 制造非易失性半导体存储器件的方法可以包括在半导体衬底上形成焊盘氧化物层图案和掩模图案，在半导体衬底内形成沟槽，掩模图案用作蚀刻掩模，顺序地形成第一器件隔离层 以及可以填充沟槽的第二器件隔离层，通过去除掩模图案形成开口以暴露焊盘氧化物层图案的上表面和第二器件隔离层的侧壁，以及形成具有 通过同时去除衬垫氧化物层图案和由开口暴露的第二器件隔离层的侧壁部分，宽度大于开口宽度。

公开(公告)号：US07560386B2

公开(公告)日：2009-07-14

申请号：US11714850

申请日：2007-03-07

申请人： Ji-hoon Cha ,  Woo-gwam Shim ,  Dong-gyun Han ,  Chang-ki Hong ,  Seung-pil Chung

发明人： Ji-hoon Cha ,  Woo-gwam Shim ,  Dong-gyun Han ,  Chang-ki Hong ,  Seung-pil Chung

IPC分类号： H01L21/311

CPC分类号： H01L21/76224 ,  Y10S438/954

摘要： A method of manufacturing a nonvolatile semiconductor memory device may include forming a pad oxide layer pattern and a mask pattern on a semiconductor substrate, forming a trench within the semiconductor substrate with the mask pattern functioning as an etching mask, sequentially forming a first device isolation layer and a second device isolation layer that may fill the trench, forming an opening by removing the mask pattern to expose an upper surface of the pad oxide layer pattern and a sidewall of the second device isolation layer, and forming a floating gate forming region having a width wider than the opening by simultaneously removing the pad oxide layer pattern and a sidewall portion of the second device isolation layer exposed by the opening.

摘要翻译： 制造非易失性半导体存储器件的方法可以包括在半导体衬底上形成焊盘氧化物层图案和掩模图案，在半导体衬底内形成沟槽，掩模图案用作蚀刻掩模，顺序地形成第一器件隔离层 以及可以填充沟槽的第二器件隔离层，通过去除掩模图案形成开口以暴露焊盘氧化物层图案的上表面和第二器件隔离层的侧壁，以及形成具有 通过同时去除衬垫氧化物层图案和由开口暴露的第二器件隔离层的侧壁部分，宽度大于开口宽度。

公开(公告)号：US20150162221A1

公开(公告)日：2015-06-11

申请号：US14580513

申请日：2014-12-23

申请人： Hyo-San Lee ,  Chang-ki Hong ,  Kun-tack Lee ,  Jeong-nam Han

发明人： Hyo-San Lee ,  Chang-ki Hong ,  Kun-tack Lee ,  Jeong-nam Han

IPC分类号： H01L21/67 ,  H01J37/32

CPC分类号： H01L21/67017 ,  H01J37/32449 ,  H01J37/32467 ,  H01J37/32715 ,  H01J37/32743 ,  H01J37/32816 ,  H01J2237/334 ,  H01J2237/335 ,  H01L21/67028 ,  H01L21/67069 ,  H01L21/67276 ,  Y10T137/2931 ,  Y10T137/4673

摘要： Provided are an apparatus and method for treating wafers using a supercritical fluid. The wafer treatment apparatus includes a plurality of chambers; a first supply supplying a first fluid in a supercritical state; a second supply supplying a mixture of the first fluid and a second fluid; a plurality of first and second valves; and a controller selecting a first chamber of the plurality of chambers for wafer treatment to control the open/closed state of each of the plurality of first valves so that the first fluid can be supplied only to the first chamber of the plurality of chambers and selecting a second chamber of the plurality of chambers to control the open/closed state of each of the plurality of second valves so that the mixture of the first fluid and a second fluid can be supplied only to the second chamber of the plurality of chambers. The wafer treatment method involves performing a predetermined treatment such as etching, cleaning or drying on wafers within only one of the plurality of chambers, followed by wafer treatment on the succeeding chamber, and thus allowing for sequential wafer treatment within each of the plurality of chambers.

摘要翻译： 提供了一种使用超临界流体处理晶片的设备和方法。 晶片处理装置包括多个室; 供应超临界状态的第一流体的第一供应源; 供应第一流体和第二流体的混合物的第二供应源; 多个第一和第二阀; 以及控制器，选择用于晶片处理的多个室的第一室，以控制多个第一阀中的每一个的打开/关闭状态，使得第一流体仅能够供应到多个室的第一室，并且选择 多个室中的第二室，用于控制多个第二阀中的每一个的打开/关闭状态，使得第一流体和第二流体的混合物只能供应到多个室的第二室。 晶片处理方法包括对多个室内的仅一个中的晶片进行蚀刻，清洗或干燥等预定处理，然后在后续室进行晶片处理，从而允许在多个室内进行顺序晶片处理 。