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    Method of fabricating semiconductor device including a recessed channel
    2.
    发明授权
    Method of fabricating semiconductor device including a recessed channel 有权
    制造包括凹陷通道的半导体器件的方法

    公开(公告)号：US08835257B2

    公开(公告)日：2014-09-16

    申请号：US13312176

    申请日：2011-12-06

    申请人： Young-Pil Kim ,  Hyung-Ik Lee ,  Woo-Sung Jeon ,  Ki-Hong Kim ,  Jung-Yun Won ,  In-Sun Jung

    发明人： Young-Pil Kim ,  Hyung-Ik Lee ,  Woo-Sung Jeon ,  Ki-Hong Kim ,  Jung-Yun Won ,  In-Sun Jung

    IPC分类号： H01L21/762 ,  H01L27/105 ,  H01L27/108

    CPC分类号： H01L27/1052 ,  H01L21/76224 ,  H01L27/10876

    摘要： A method including forming an isolation trench; forming first and second liners on the isolation trench; filling the isolation trench an insulating material to form an isolation region and an active region; forming a preliminary gate trench including a first region across the isolation region to expose the first liner, the second liner, and the insulating material, and a second region across the active region to expose a portion of the substrate, the first region having a first sidewall with a planar shape, and the second region having a second sidewall with a concave central area such that an interface between the first and second regions has a pointed portion; removing a portion of the first liner exposed by the first region to form a dent having a first depth by which the pointed portion protrudes; removing the pointed portion to form a gate trench; and forming a gate electrode.

    摘要翻译： 一种包括形成隔离沟槽的方法; 在隔离槽上形成第一和第二衬垫; 将绝缘沟槽填充绝缘材料以形成隔离区域和有源区域; 形成包括隔离区域的第一区域的初步栅极沟槽，以露出第一衬垫，第二衬垫和绝缘材料，以及横跨有源区域的第二区域以暴露衬底的一部分，第一区域具有第一 侧壁具有平面形状，并且所述第二区域具有第二侧壁，所述第二侧壁具有凹形中心区域，使得所述第一和第二区域之间的界面具有尖锐部分; 去除由所述第一区域暴露的所述第一衬垫的一部分以形成具有所述尖部突出的第一深度的凹陷; 去除尖部以形成栅沟; 并形成栅电极。

    Methods of fabricating semiconductor devices including elevated source and drain regions
    4.
    发明授权
    Methods of fabricating semiconductor devices including elevated source and drain regions 有权
    制造包括升高的源极和漏极区域的半导体器件的方法

    公开(公告)号：US07867865B2

    公开(公告)日：2011-01-11

    申请号：US12166575

    申请日：2008-07-02

    申请人： Jin-Bum Kim ,  Young-Pil Kim ,  Jung-Yun Won ,  Hion-Suck Baik ,  Jun-Ho Lee

    发明人： Jin-Bum Kim ,  Young-Pil Kim ,  Jung-Yun Won ,  Hion-Suck Baik ,  Jun-Ho Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823456 ,  H01L21/823418 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/4236 ,  H01L29/66621

    摘要： Methods of fabricating semiconductor devices are provided. A substrate having active patterns and isolating layer patterns is prepared. Each of the isolating layer patterns has an upper surface higher than that of each of the active patterns. A spacer layer having a uniform thickness is formed on the substrate. The spacer layer is etched to form a spacer on a sidewall of each of the isolating layer patterns. A gate structure is formed on each of the active patterns. A selective epitaxial growth (SEG) process is performed on the active patterns having the gate structure to form isolated epitaxial layers that have upper surfaces higher than those of the isolating layer patterns, on the active patterns. Related semiconductor devices are also provided.

    摘要翻译： 提供制造半导体器件的方法。 制备具有活性图案和隔离层图案的基板。 每个隔离层图案的上表面高于每个活动图案的上表面。 在基板上形成具有均匀厚度的间隔层。 蚀刻间隔层以在每个隔离层图案的侧壁上形成间隔物。 在每个有源图案上形成栅极结构。 对具有栅极结构的有源图案进行选择性外延生长（SEG）处理，以在活性图案上形成具有高于绝缘层图案的上表面的隔离的外延层。 还提供了相关的半导体器件。

    Semiconductor Devices Including Elevated Source and Drain Regions and Methods of Fabricating the Same
    5.
    发明申请
    Semiconductor Devices Including Elevated Source and Drain Regions and Methods of Fabricating the Same 有权
    包括提升源和排水区的半导体器件及其制造方法

    公开(公告)号：US20090008717A1

    公开(公告)日：2009-01-08

    申请号：US12166575

    申请日：2008-07-02

    申请人： Jin-Bum Kim ,  Young-Pil Kim ,  Jung-Yun Won ,  Hion-Suck Baik ,  Jun-Ho Lee

    发明人： Jin-Bum Kim ,  Young-Pil Kim ,  Jung-Yun Won ,  Hion-Suck Baik ,  Jun-Ho Lee

    IPC分类号： H01L21/336 ,  H01L27/088

    CPC分类号： H01L21/823456 ,  H01L21/823418 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/4236 ,  H01L29/66621

    摘要： Methods of fabricating semiconductor devices are provided. A substrate having active patterns and isolating layer patterns is prepared. Each of the isolating layer patterns has an upper surface higher than that of each of the active patterns. A spacer layer having a uniform thickness is formed on the substrate. The spacer layer is etched to form a spacer on a sidewall of each of the isolating layer patterns. A gate structure is formed on each of the active patterns. A selective epitaxial growth (SEG) process is performed on the active patterns having the gate structure to form isolated epitaxial layers that have upper surfaces higher than those of the isolating layer patterns, on the active patterns. Related semiconductor devices are also provided.

    摘要翻译： 提供制造半导体器件的方法。 制备具有活性图案和隔离层图案的基板。 每个隔离层图案的上表面高于每个活动图案的上表面。 在基板上形成具有均匀厚度的间隔层。 蚀刻间隔层以在每个隔离层图案的侧壁上形成间隔物。 在每个有源图案上形成栅极结构。 对具有栅极结构的有源图案进行选择性外延生长（SEG）处理，以在活性图案上形成具有高于绝缘层图案的上表面的隔离的外延层。 还提供了相关的半导体器件。

    Semiconductor Devices Including Elevated Source and Drain Regions
    6.
    发明申请
    Semiconductor Devices Including Elevated Source and Drain Regions 有权
    包括高压源和排水区的半导体器件

    公开(公告)号：US20110073941A1

    公开(公告)日：2011-03-31

    申请号：US12962061

    申请日：2010-12-07

    申请人： Jin Bum Kim ,  Young-Pil Kim ,  Jung-Yun Won ,  Hion-Suck Baik ,  Jun-Ho Lee

    发明人： Jin Bum Kim ,  Young-Pil Kim ,  Jung-Yun Won ,  Hion-Suck Baik ,  Jun-Ho Lee

    IPC分类号： H01L27/088

    CPC分类号： H01L21/823456 ,  H01L21/823418 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/4236 ,  H01L29/66621

    摘要： Methods of fabricating semiconductor devices are provided. A substrate having active patterns and isolating layer patterns is prepared. Each of the isolating layer patterns has an upper surface higher than that of each of the active patterns. A spacer layer having a uniform thickness is formed on the substrate. The spacer layer is etched to form a spacer on a sidewall of each of the isolating layer patterns. A gate structure is formed on each of the active patterns. A selective epitaxial growth (SEG) process is performed on the active patterns having the gate structure to form isolated epitaxial layers that have upper surfaces higher than those of the isolating layer patterns, on the active patterns. Related semiconductor devices are also provided.

    摘要翻译： 提供制造半导体器件的方法。 制备具有活性图案和隔离层图案的基板。 每个隔离层图案的上表面高于每个活动图案的上表面。 在基板上形成具有均匀厚度的间隔层。 蚀刻间隔层以在每个隔离层图案的侧壁上形成间隔物。 在每个有源图案上形成栅极结构。 对具有栅极结构的有源图案进行选择性外延生长（SEG）处理，以在活性图案上形成具有高于绝缘层图案的上表面的隔离的外延层。 还提供了相关的半导体器件。

    Semiconductor devices including elevated source and drain regions
    7.
    发明授权
    Semiconductor devices including elevated source and drain regions 有权
    半导体器件包括升高的源极和漏极区域

    公开(公告)号：US08552494B2

    公开(公告)日：2013-10-08

    申请号：US12962061

    申请日：2010-12-07

    申请人： Jin-Bum Kim ,  Young-Pil Kim ,  Jung-Yun Won ,  Hion-Suck Baik ,  Jun-Ho Lee

    发明人： Jin-Bum Kim ,  Young-Pil Kim ,  Jung-Yun Won ,  Hion-Suck Baik ,  Jun-Ho Lee

    IPC分类号： H01L27/088

    CPC分类号： H01L21/823456 ,  H01L21/823418 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/4236 ,  H01L29/66621

    摘要： Methods of fabricating semiconductor devices are provided. A substrate having active patterns and isolating layer patterns is prepared. Each of the isolating layer patterns has an upper surface higher than that of each of the active patterns. A spacer layer having a uniform thickness is formed on the substrate. The spacer layer is etched to form a spacer on a sidewall of each of the isolating layer patterns. A gate structure is formed on each of the active patterns. A selective epitaxial growth (SEG) process is performed on the active patterns having the gate structure to form isolated epitaxial layers that have upper surfaces higher than those of the isolating layer patterns, on the active patterns. Related semiconductor devices are also provided.

    摘要翻译： 提供制造半导体器件的方法。 制备具有活性图案和隔离层图案的基板。 每个隔离层图案的上表面高于每个活动图案的上表面。 在基板上形成具有均匀厚度的间隔层。 蚀刻间隔层以在每个隔离层图案的侧壁上形成间隔物。 在每个有源图案上形成栅极结构。 对具有栅极结构的有源图案进行选择性外延生长（SEG）处理，以在活性图案上形成具有高于绝缘层图案的上表面的隔离的外延层。 还提供了相关的半导体器件。

    METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    8.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR DEVICE 审中-公开
    制造半导体器件的方法

    公开(公告)号：US20120135576A1

    公开(公告)日：2012-05-31

    申请号：US13242784

    申请日：2011-09-23

    申请人： Hyun-Jung Lee ,  Young-Pil Kim ,  Jin-Bum Kim ,  Sang-Bom Kang ,  Kwan-Yong Lim

    发明人： Hyun-Jung Lee ,  Young-Pil Kim ,  Jin-Bum Kim ,  Sang-Bom Kang ,  Kwan-Yong Lim

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66545 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/7849

    摘要： Provided are a semiconductor device and a method of fabricating a semiconductor device. The method includes providing a substrate having a channel region; forming a gate structure, which comprises a dummy gate pattern, on the substrate; forming first and second trenches by recessing the substrate on both sides of the gate structure, respectively; forming a first semiconductor pattern in the first and second trenches; removing the dummy gate pattern to expose a portion of the channel region; forming a recessed channel region by recessing the portion of the channel region; and forming a second semiconductor pattern in the recessed region.

    摘要翻译： 提供半导体器件和制造半导体器件的方法。 该方法包括提供具有沟道区的衬底; 在基板上形成包括虚拟栅极图案的栅极结构; 通过分别在栅极结构的两侧凹陷衬底来形成第一和第二沟槽; 在所述第一和第二沟槽中形成第一半导体图案; 去除伪栅极图案以暴露沟道区域的一部分; 通过使所述通道区域的所述部分凹陷来形成凹陷通道区域; 以及在凹陷区域中形成第二半导体图案。

    Method of manufacturing a semiconductor device
    10.
    发明授权
    Method of manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US08877583B2

    公开(公告)日：2014-11-04

    申请号：US13728622

    申请日：2012-12-27

    申请人： Jin-Bum Kim ,  Young-Pil Kim ,  Kwan-Heum Lee ,  Sun-Ghil Lee

    发明人： Jin-Bum Kim ,  Young-Pil Kim ,  Kwan-Heum Lee ,  Sun-Ghil Lee

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/285 ,  H01L21/768 ,  H01L49/02

    CPC分类号： H01L21/285 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76889 ,  H01L27/10855 ,  H01L28/91

    摘要： In a method of forming an ohmic layer of a DRAM device, the metal silicide layer between the storage node contact plug and the lower electrode of a capacitor is formed as the ohmic layer by a first heat treatment under a first temperature and an instantaneous second heat treatment under a second temperature higher than the first temperature. Thus, the metal silicide layer has a thermo-stable crystal structure and little or no agglomeration occurs on the metal silicide layer in the high temperature process. Accordingly, the sheet resistance of the ohmic layer may not increase in spite of the subsequent high temperature process.

    摘要翻译： 在形成DRAM器件的欧姆层的方法中，通过在第一温度和瞬时第二次加热下的第一次热处理将存储节点接触插塞和电容器的下部电极之间的金属硅化物层形成为欧姆层 在比第一温度高的第二温度下进行处理。 因此，金属硅化物层具有热稳定的晶体结构，并且在高温工艺中在金属硅化物层上几乎或不发生聚集。 因此，尽管随后的高温处理，欧姆层的薄层电阻也可能不增加。