公开(公告)号：US09972716B2

公开(公告)日：2018-05-15

申请号：US14826439

申请日：2015-08-14

申请人： Jin-Bum Kim ,  Seok-Hoon Kim ,  Chul Kim ,  Kwan-Heum Lee ,  Byeong-Chan Lee ,  Cho-Eun Lee ,  Su-Jin Jung ,  Bon-Young Koo

发明人： Jin-Bum Kim ,  Seok-Hoon Kim ,  Chul Kim ,  Kwan-Heum Lee ,  Byeong-Chan Lee ,  Cho-Eun Lee ,  Su-Jin Jung ,  Bon-Young Koo

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/32 ,  H01L29/66

CPC分类号： H01L29/7848 ,  H01L21/3221 ,  H01L29/165 ,  H01L29/32 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/785

摘要： Provided are semiconductor devices that include an active pattern on a substrate, first and second gate electrodes on the active pattern and arranged in a first direction relative to one another and a first source/drain region in a first trench that extends into the active pattern between the first and second gate electrodes. The first source/drain region includes a first epitaxial layer that is configured to fill the first trench and that includes at least one plane defect that originates at a top portion of the first epitaxial layer and extends towards a bottom portion of the first epitaxial layer.

公开(公告)号：US09368495B2

公开(公告)日：2016-06-14

申请号：US14576368

申请日：2014-12-19

申请人： Seok-Hoon Kim ,  Jin-Bum Kim ,  Kwan-Heum Lee ,  Byeong-Chan Lee ,  Cho-Eun Lee ,  Jin-Hee Han ,  Bon-Young Koo

发明人： Seok-Hoon Kim ,  Jin-Bum Kim ,  Kwan-Heum Lee ,  Byeong-Chan Lee ,  Cho-Eun Lee ,  Jin-Hee Han ,  Bon-Young Koo

IPC分类号： H01L21/00 ,  H01L27/088 ,  H01L27/02 ,  H01L29/78

CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785

摘要： A semiconductor device includes a substrate, a first active fin and a second active fin on the substrate, respectively, a plurality of first epitaxial layers on the first active fin and on the second active fin, respectively, a plurality of second epitaxial layers on the plurality of first epitaxial layers, a bridge layer connecting the plurality of second epitaxial layers to each other, and a third epitaxial layer on the bridge layer.

摘要翻译： 半导体器件分别在衬底上包括衬底，第一有源鳍片和第二有源鳍片，分别在第一有源鳍片和第二有源鳍片上的多个第一外延层，多个第二外延层， 多个第一外延层，将多个第二外延层彼此连接的桥接层以及桥接层上的第三外延层。

公开(公告)号：US09595611B2

公开(公告)日：2017-03-14

申请号：US14262712

申请日：2014-04-26

申请人： Seok-Hoon Kim ,  Bon-Young Koo ,  Nam-Kyu Kim ,  Woo-Bin Song ,  Byeong-Chan Lee ,  Su-Jin Jung

发明人： Seok-Hoon Kim ,  Bon-Young Koo ,  Nam-Kyu Kim ,  Woo-Bin Song ,  Byeong-Chan Lee ,  Su-Jin Jung

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/12

CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681

摘要： A semiconductor device may include first and second fins formed side by side on a substrate, a first elevated doped region formed on the first fin and having a first doping concentration of impurities, a second elevated doped region formed on the second fin, and a first bridge connecting the first elevated doped region and the second elevated doped region to each other. Methods of manufacturing such a semiconductor device are also disclosed.

摘要翻译： 半导体器件可以包括在衬底上并排形成的第一和第二鳍片，形成在第一鳍片上并具有杂质的第一掺杂浓度的第一升高掺杂区域，形成在第二鳍片上的第二高掺杂区域， 将第一升高掺杂区域和第二升高掺杂区域彼此连接的桥。 还公开了制造这种半导体器件的方法。

公开(公告)号：US20110291175A1

公开(公告)日：2011-12-01

申请号：US13092239

申请日：2011-04-22

申请人： Jung-Geun Jee ,  Seok-Hoon Kim ,  Su-Jin Shin ,  Woo-Sung Lee ,  Tae-Ouk Kwon

发明人： Jung-Geun Jee ,  Seok-Hoon Kim ,  Su-Jin Shin ,  Woo-Sung Lee ,  Tae-Ouk Kwon

IPC分类号： H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11558 ,  H01L21/2807 ,  H01L21/28273 ,  H01L21/28556 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881

摘要： A non-volatile memory device includes a field region that defines an active region in a semiconductor substrate, a floating gate pattern on the active region, a dielectric layer on the floating gate pattern and a control gate on the dielectric layer. The control gate includes a first conductive pattern that has a first composition that crystallizes in a first temperature range, and a second conductive pattern that has a second composition that is different from the first composition and that crystallizes in a second temperature range that is lower than the first temperature range, the first conductive pattern being between the dielectric layer and the second conductive pattern.

摘要翻译： 非易失性存储器件包括限定半导体衬底中的有源区域的场区域，有源区域上的浮置栅极图案，浮置栅极图案上的介电层和介电层上的控制栅极。 控制栅极包括具有在第一温度范围内结晶的第一组成的第一导电图案和具有与第一组成不同的第二组成的第二导电图案，并且在低于第一组成的第二温度范围内结晶 第一温度范围，第一导电图案在介电层和第二导电图案之间。

公开(公告)号：US08633078B2

公开(公告)日：2014-01-21

申请号：US13240470

申请日：2011-09-22

申请人： Kwan-Yong Lim ,  Chung-Geun Koh ,  Sang-Bom Kang ,  Ui-Hui Kwon ,  Hyun-Jung Lee ,  Tae-Ouk Kwon ,  Seok-Hoon Kim

发明人： Kwan-Yong Lim ,  Chung-Geun Koh ,  Sang-Bom Kang ,  Ui-Hui Kwon ,  Hyun-Jung Lee ,  Tae-Ouk Kwon ,  Seok-Hoon Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/66659 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/7835 ,  H01L29/7847

摘要： A semiconductor device is formed with a gate pattern formed on a substrate, and a recrystallized region having a stacking fault defect in the substrate at one side of the gate pattern. The semiconductor device can have a reduced leakage current and improved channel conductivity.

摘要翻译： 半导体器件形成有形成在衬底上的栅极图案，以及在栅极图案一侧的衬底中具有层叠缺陷缺陷的再结晶区域。 半导体器件可以具有减小的漏电流和改善的沟道导电性。

公开(公告)号：US20120108023A1

公开(公告)日：2012-05-03

申请号：US13240470

申请日：2011-09-22

申请人： Kwan-Yong Lim ,  Chung-Geun Koh ,  Sang-Bom Kang ,  Ui-Hui Kwon ,  Hyun-Jung Lee ,  Tae-Ouk Kwon ,  Seok-Hoon Kim

发明人： Kwan-Yong Lim ,  Chung-Geun Koh ,  Sang-Bom Kang ,  Ui-Hui Kwon ,  Hyun-Jung Lee ,  Tae-Ouk Kwon ,  Seok-Hoon Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/66659 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/7835 ,  H01L29/7847

摘要： A semiconductor device is formed with a gate pattern formed on a substrate, and a recrystallized region having a stacking fault defect in the substrate at one side of the gate pattern. The semiconductor device can have a reduced leakage current and improved channel conductivity.

摘要翻译： 半导体器件形成有形成在衬底上的栅极图案，以及在栅极图案一侧的衬底中具有层叠缺陷缺陷的再结晶区域。 半导体器件可以具有减小的漏电流和改善的沟道导电性。

公开(公告)号：US08610195B2

公开(公告)日：2013-12-17

申请号：US13092239

申请日：2011-04-22

申请人： Jung-Geun Jee ,  Seok-Hoon Kim ,  Su-Jin Shin ,  Woo-Sung Lee ,  Tae-Ouk Kwon

发明人： Jung-Geun Jee ,  Seok-Hoon Kim ,  Su-Jin Shin ,  Woo-Sung Lee ,  Tae-Ouk Kwon

IPC分类号： H01L29/788

CPC分类号： H01L27/11558 ,  H01L21/2807 ,  H01L21/28273 ,  H01L21/28556 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881

摘要： A non-volatile memory device includes a field region that defines an active region in a semiconductor substrate, a floating gate pattern on the active region, a dielectric layer on the floating gate pattern and a control gate on the dielectric layer. The control gate includes a first conductive pattern that has a first composition that crystallizes in a first temperature range, and a second conductive pattern that has a second composition that is different from the first composition and that crystallizes in a second temperature range that is lower than the first temperature range, the first conductive pattern being between the dielectric layer and the second conductive pattern.

公开(公告)号：US20120034749A1

公开(公告)日：2012-02-09

申请号：US13197658

申请日：2011-08-03

申请人： Kwan-Yong LIM ,  Chung-Geun Koh ,  Hyun-Jung Lee ,  Tae-Ouk Kwon ,  Seok-Hoon Kim ,  Tae-Ho Cha

发明人： Kwan-Yong LIM ,  Chung-Geun Koh ,  Hyun-Jung Lee ,  Tae-Ouk Kwon ,  Seok-Hoon Kim ,  Tae-Ho Cha

IPC分类号： H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/823807 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7847

摘要： A method of manufacturing a semiconductor device can be provided by forming a gate structure on a substrate and forming a diffusion barrier layer on the gate structure and the substrate, A stress layer can be formed on the diffusion barrier layer comprising a metal nitride or a metal oxide having a concentration of nitrogen or oxygen associated therewith. The stress layer can be heated to transform the stress layer into a tensile stress layer to reduce the concentration of the nitrogen or the oxygen in the stress layer. The tensile stress layer and the diffusion barrier layer can be removed.

摘要翻译： 可以通过在衬底上形成栅极结构并在栅极结构和衬底上形成扩散阻挡层来提供制造半导体器件的方法.A应力层可以形成在包含金属氮化物或金属的扩散阻挡层上 具有与其相关联的氮或氧浓度的氧化物。 应力层可以被加热以将应力层转变成拉伸应力层，以减小应力层中的氮或氧的浓度。 可以去除拉伸应力层和扩散阻挡层。

公开(公告)号：US20070193515A1

公开(公告)日：2007-08-23

申请号：US11703621

申请日：2007-02-07

申请人： Hyeong-Tag Jeon ,  In-Hoe Kim ,  Seok-Hoon Kim ,  Chin-Wook Chung ,  Sahng-Kyoo Lee

发明人： Hyeong-Tag Jeon ,  In-Hoe Kim ,  Seok-Hoon Kim ,  Chin-Wook Chung ,  Sahng-Kyoo Lee

IPC分类号： C23F1/00 ,  C23C16/00

CPC分类号： H05H1/46 ,  H01J37/3211 ,  H01J37/32357 ,  H01J37/3244

摘要： Provided is an apparatus for generating remote plasma. The apparatus includes an RF antenna disposed in regard to a chamber, a plasma generating unit formed in an uppermost portion of the chamber, wherein a plurality of plasma generation gas introduction pipes are communicated with the plasma generating unit, a first shower head disposed below the plasma generating unit, and having a plurality of first plasma guide holes, a second shower head disposed below the first shower head, and having a plurality of source/purge gas guide holes and a plurality of second plasma guide holes directly connected to the respective first plasma guide holes, and a source/purge gas introduction unit disposed between the first and second shower heads, wherein a plurality of source/purge gas introduction pipes are uniformly communicated with the source/purge gas introduction unit.

摘要翻译： 提供了一种用于产生远程等离子体的装置。 该装置包括：关于腔室设置的RF天线，形成在腔室的最上部的等离子体产生单元，其中多个等离子体产生气体导入管与等离子体产生单元连通;第一淋浴喷头， 等离子体发生单元，并具有多个第一等离子体引导孔，设置在第一喷淋头下方的第二喷淋头，并且具有多个源/吹扫气体引导孔和多个第二等离子体引导孔，其直接连接到相应的第一等离子体引导孔 等离子体引导孔和设置在第一和第二喷淋头之间的源/净化气体引入单元，其中多个源/净化气体引入管与源/净化气体导入单元均匀地连通。

公开(公告)号：US08101480B1

公开(公告)日：2012-01-24

申请号：US12944774

申请日：2010-11-12

申请人： Seok-Hoon Kim ,  Chung-Geun Koh ,  Kwan-Yong Lim ,  Hyun-Jung Lee ,  Tae-Ouk Kwon ,  Sang-Bom Kang

发明人： Seok-Hoon Kim ,  Chung-Geun Koh ,  Kwan-Yong Lim ,  Hyun-Jung Lee ,  Tae-Ouk Kwon ,  Sang-Bom Kang

IPC分类号： H01L21/8238 ,  H01L21/02

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/7848

摘要： A method of forming a transistor induces stress in the channel region using a stress memorization technique (SMT). Impurities are implanted into a substrate adjacent a gate electrode structure to produce an amorphous region adjacent the channel region. The amorphous region is then recrystallized by forming a metal-oxide layer over the amorphous region, and then thermally treating the same. The crystallization creates compressive stress in the amorphous region. As a result, stress is induced in the channel region of the substrate located under the gate electrode structure.

摘要翻译： 晶体管的形成方法利用应力记忆技术（SMT）在沟道区域中产生应力。 将杂质注入邻近栅电极结构的衬底中以产生邻近沟道区的非晶区。 然后通过在无定形区域上形成金属氧化物层使非晶区域重结晶，然后对其进行热处理。 结晶在非晶区域产生压应力。 结果，在位于栅电极结构下方的衬底的沟道区域中产生应力。