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    Window-type ball grid array semiconductor package
    1.
    发明授权
    Window-type ball grid array semiconductor package 有权
    窗型球栅阵列半导体封装

    公开(公告)号：US06822337B2

    公开(公告)日：2004-11-23

    申请号：US10261834

    申请日：2002-09-30

    申请人： Jin-Chuan Bai

    发明人： Jin-Chuan Bai

    IPC分类号： H01C2348

    CPC分类号： H01L23/3135 ,  H01L23/13 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599

    摘要： A window-type ball grid array (WBGA) semiconductor package is proposed. A substrate is formed with an opening and a tape attach area around the opening. A polyimide tape having an aperture is applied over the tape attach area, allowing the aperture to be aligned with the opening of the substrate. A chip is mounted over the polyimide tape and electrically connected to the substrate via the opening by bonding wires, wherein the polyimide tape is interposed between the chip and the substrate so as not to leave any gaps between the chip and the substrate. A first encapsulant is formed to fill the opening and encapsulate the bonding wires. A second encapsulant is fabricated to encapsulate the chip. With no gaps between the chip and the substrate, the chip is firmly supported on the substrate during a molding process for fabricating the second encapsulant, thereby preventing chip cracks from occurrence.

    摘要翻译： 提出了一种窗型球栅阵列（WBGA）半导体封装。 衬底形成有开口和围绕开口的带附着区域。 具有孔径的聚酰亚胺带被施加在带附着区域上，允许孔与基板的开口对准。 将芯片安装在聚酰亚胺带上，通过接合线通过开口与基板电连接，其中聚酰亚胺带插入在芯片和基板之间，以便在芯片和基板之间不留下任何间隙。 形成第一密封剂以填充开口并封装接合线。 制造第二密封剂以封装芯片。 在芯片和基板之间没有间隙的情况下，在用于制造第二密封剂的模制工艺期间，芯片牢固地支撑在基板上，从而防止芯片发生裂纹。

    Semiconductor device and method for fabricating the same
    2.
    发明授权
    Semiconductor device and method for fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US06790712B2

    公开(公告)日：2004-09-14

    申请号：US10214758

    申请日：2002-08-09

    申请人： Jin-Chuan Bai

    发明人： Jin-Chuan Bai

    IPC分类号： H01L2144

    CPC分类号： H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/50 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48471 ,  H01L2224/85001 ,  H01L2924/01013 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00014 ,  H01L2924/00012

    摘要： A semiconductor device is proposed, in which a chip is placed in an opening penetratingly formed in a substrate in a manner as not to come into contact with the substrate, and an encapsulant formed on the substrate fills up the opening for encapsulating the chip. This arrangement of the chip accommodated in the substrate therefore reduces the overall height of the semiconductor device. Moreover, a plurality of conductive elements disposed on the substrate are also encapsulated by the encapsulant in a manner that, bottom sides of the conductive elements are exposed to outside of the encapsulant, and coplanarly positioned with a bottom side of the encapsulant. This therefore provides good planarity for a bottom side of the semiconductor device, allowing the semiconductor device to be well electrically connected to external devices. A method for fabricating the foregoing semiconductor device is also proposed.

    摘要翻译： 提出了一种半导体器件，其中以不与基板接触的方式将芯片置于穿透形成在基板中的开口中，并且形成在基板上的密封剂填满用于封装芯片的开口。 容纳在基板中的芯片的这种布置因此降低了半导体器件的整体高度。 此外，设置在基板上的多个导电元件也被密封剂封装，使得导电元件的底侧暴露于密封剂的外部，并与密封剂的底侧共面定位。 因此，这为半导体器件的底侧提供良好的平面性，允许半导体器件与外部器件良好地电连接。 还提出了制造上述半导体器件的方法。

    Semiconductor device and method for fabricating the same
    4.
    发明授权
    Semiconductor device and method for fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US06964888B2

    公开(公告)日：2005-11-15

    申请号：US10900134

    申请日：2004-07-28

    申请人： Jin-Chuan Bai

    发明人： Jin-Chuan Bai

    IPC分类号： H01L21/56 ,  H01L21/68 ,  H01L23/13 ,  H01L23/31 ,  H01L21/44

    CPC分类号： H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/50 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48471 ,  H01L2224/85001 ,  H01L2924/01013 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00014 ,  H01L2924/00012

    摘要： A semiconductor device is proposed, in which a chip is placed in an opening penetratingly formed in a substrate in a manner as not to come into contact with the substrate, and an encapsulant formed on the substrate fills up the opening for encapsulating the chip. This arrangement of the chip accommodated in the substrate therefore reduces the overall height of the semiconductor device. Moreover, a plurality of conductive elements disposed on the substrate are also encapsulated by the encapsulant in a manner that, bottom sides of the conductive elements are exposed to outside of the encapsulant, and coplanarly positioned with a bottom side of the encapsulant. This therefore provides good planarity for a bottom side of the semiconductor device, allowing the semiconductor device to be well electrically connected to external devices. A method for fabricating the foregoing semiconductor device is also proposed.

    摘要翻译： 提出了一种半导体器件，其中以不与基板接触的方式将芯片置于穿透形成在基板中的开口中，并且形成在基板上的密封剂填满用于封装芯片的开口。 容纳在基板中的芯片的这种布置因此降低了半导体器件的整体高度。 此外，设置在基板上的多个导电元件也被密封剂封装，使得导电元件的底侧暴露于密封剂的外部，并与密封剂的底侧共面定位。 因此，这为半导体器件的底侧提供良好的平面性，允许半导体器件与外部器件良好地电连接。 还提出了制造上述半导体器件的方法。

    Test fixture for semiconductor package and test method of using the same
    5.
    发明授权
    Test fixture for semiconductor package and test method of using the same 失效
    用于半导体封装的测试夹具及其使用的测试方法

    公开(公告)号：US06859056B2

    公开(公告)日：2005-02-22

    申请号：US10176147

    申请日：2002-06-20

    申请人： Jin-Chuan Bai ,  Huan-Ping Su ,  Soon-Aik Lu

    发明人： Jin-Chuan Bai ,  Huan-Ping Su ,  Soon-Aik Lu

    IPC分类号： G01R1/04 ,  G01R31/02

    CPC分类号： G01R1/0408

    摘要： A test fixture for semiconductor packages and a test method of using the test fixture are proposed. The test fixture is composed of a circuit board, an interposer and a covering member. The circuit board is used to accommodate semiconductor packages and electrically connect the semiconductor packages to a test device. The interposer is mounted on the circuit board, and formed with through holes for receiving the semiconductor packages therein. The covering member is attached onto the interposer, and provided with elastic mechanisms for holding the semiconductor packages in position. By using the test fixture, semiconductor packages can be firmly coupled to the test device where functional tests are performed.

    摘要翻译： 提出了半导体封装的测试夹具和使用测试夹具的测试方法。 测试夹具由电路板，插入件和覆盖件构成。 电路板用于容纳半导体封装并将半导体封装电连接到测试装置。 插入器安装在电路板上，并形成有用于在其中接收半导体封装的通孔。 覆盖构件附接到插入件上，并且设置有用于将半导体封装保持在适当位置的弹性机构。 通过使用测试夹具，半导体封装可以牢固地耦合到执行功能测试的测试设备。

    Window-type semiconductor package and fabrication method thereof
    6.
    发明授权
    Window-type semiconductor package and fabrication method thereof 有权
    窗型半导体封装及其制造方法

    公开(公告)号：US06710434B1

    公开(公告)日：2004-03-23

    申请号：US10261833

    申请日：2002-09-30

    申请人： Jin-Chuan Bai

    发明人： Jin-Chuan Bai

    IPC分类号： H01L2306

    CPC分类号： H01L23/3114 ,  H01L23/13 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/4824 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2224/05599

    摘要： A window-type semiconductor package and a fabrication method thereof are provided. A substrate having an opening is mounted with at least a chip in a manner that, a conductive area of an active surface of the chip is exposed to the opening, and electrically connected to the substrate by bonding wires formed through the opening. A non-conductive material is applied over the conductive area of the chip. An upper encapsulant is formed to encapsulate the chip, and a lower encapsulant is formed to encapsulate the bonding wires and the non-conductive material. The non-conductive material interposed between the chip and the lower encapsulant helps prevent the chip from cracking at end portions thereof due to shrinkage of the lower encapsulant, and also helps secure the bonding wires in position within the opening of the substrate without causing wire-sweeping, such that reliability and yield of the semiconductor package can be assured.

    摘要翻译： 提供了一种窗型半导体封装及其制造方法。 具有开口的基板至少安装有芯片，芯片的有源表面的导电区域暴露于开口，并且通过开口形成的接合线电连接到基板。 非导电材料被施加在芯片的导电区域上。 形成上部密封剂以封装芯片，并且形成下部密封剂以封装接合线和非导电材料。 介于芯片和下部密封剂之间的非导电材料有助于防止芯片由于下部密封剂的收缩而在其端部开裂，并且还有助于将接合线固定在衬底的开口内的适当位置， 可以确保半导体封装的可靠性和产量。

    Fabrication method of circuit board
    7.
    发明授权
    Fabrication method of circuit board 失效
    电路板制作方法

    公开(公告)号：US06968613B2

    公开(公告)日：2005-11-29

    申请号：US10176122

    申请日：2002-06-20

    申请人： Chung-Che Tsai ,  Jin-Chuan Bai

    发明人： Chung-Che Tsai ,  Jin-Chuan Bai

    IPC分类号： H05K3/28 ,  H01K3/10

    CPC分类号： H05K3/28 ,  H05K2201/0959 ,  H05K2203/0582 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49171

    摘要： A fabrication method of a circuit board is proposed, wherein a core layer is formed with a plurality of conductive traces, and photo resist is respectively applied on terminals of the conductive traces. Then, a non-solderable material is applied over the core layer as to cover the conductive traces except for the insulating material, and the non-solderable material is adapted to be surface-flush with the insulating material, allowing the insulating material to be exposed from the non-solderable material. Finally, the insulating material is removed from the core layer to expose the terminals of the conductive traces, wherein the exposed terminals are used as bond pads or bond fingers where solder balls, solder bumps or bonding wires can be bonded. This circuit board is cost-effectively fabricated by simplified processes, and beneficial in precisely exposing bond pads or bond fingers, thereby significantly improving yield of fabricated circuit boards.

    摘要翻译： 提出了一种电路板的制造方法，其中芯层形成有多个导电迹线，并且将光致抗蚀剂分别施加在导电迹线的端子上。 然后，在芯层上施加不可焊接的材料以覆盖导电迹线，绝缘材料除外，并且不可焊接材料适于与绝缘材料表面齐平，从而使绝缘材料暴露 来自不可焊接材料。 最后，从芯层去除绝缘材料以露出导电迹线的端子，其中暴露的端子用作可焊接焊球，焊料凸块或接合线的接合焊盘或接合指状物。 该电路板通过简化的工艺成本有效地制造，并且有益于精确地暴露接合焊盘或接合指，从而显着提高制造的电路板的产量。

    Fabrication method for circuit board
    8.
    发明授权
    Fabrication method for circuit board 失效
    电路板制作方法

    公开(公告)号：US06740540B2

    公开(公告)日：2004-05-25

    申请号：US10170664

    申请日：2002-06-12

    申请人： Chung-Che Tsai ,  Jin-Chuan Bai

    发明人： Chung-Che Tsai ,  Jin-Chuan Bai

    IPC分类号： H01L2144

    CPC分类号： H05K3/28 ,  H05K2203/0264 ,  H05K2203/0278 ,  H05K2203/0582 ,  H05K2203/066 ,  Y10T29/49124

    摘要： A fabrication method for a circuit board is proposed, wherein a core layer is formed with a plurality of conductive traces, and photo resist is applied on terminals of the conductive traces. A non-solderable material is peelably applied over a support member, and attached to the core layer to cover the conductive traces, wherein adhesion between the support member and the non-solderable material is smaller than adhesion between the non-solderable material and the core layer. Then, the support member is peeled to expose the non-solderable material; further, the non-solderable material is partly removed to expose the photo resist. Finally, the photo resist is etched away to expose the terminals of the conductive traces. The exposed terminals serve as bond pads or fingers where solder balls, bumps or wires are bonded for electrical connection purpose.

    摘要翻译： 提出了一种用于电路板的制造方法，其中芯层形成有多个导电迹线，并且光刻胶施加在导电迹线的端子上。 不可焊接材料可剥离地施加在支撑构件上，并且附接到芯层以覆盖导电迹线，其中支撑构件和不可焊接材料之间的粘附小于不可焊材料和芯之间的粘附 层。 然后，将支撑构件剥离以露出不可焊接材料; 此外，部分地去除不可焊接材料以暴露光致抗蚀剂。 最后，蚀刻光刻胶以露出导电迹线的端子。 露出的端子用作接合焊盘或手指，其中焊球，凸块或导线被接合用于电连接目的。