公开(公告)号：US20070020937A1

公开(公告)日：2007-01-25

申请号：US11502614

申请日：2006-08-09

申请人： Jin-Yuan Chen ,  Frank Hooshdaran ,  Dragan Podlesnik

发明人： Jin-Yuan Chen ,  Frank Hooshdaran ,  Dragan Podlesnik

IPC分类号： H01L21/302

CPC分类号： H01J37/321 ,  H01J37/32706

摘要： A method and apparatus for selectively controlling a plasma in a processing chamber during wafer processing. The method includes providing process gasses into the chamber over a wafer to be processed, and providing high frequency RF power to a plasma generating element and igniting the process gases into the plasma. Modulated RF power is coupled to a biasing element, and wafer processing is performed according to a particular processing recipe. The apparatus includes a biasing element disposed in the chamber and adapted to support a wafer, and a plasma generating element disposed over the biasing element and wafer. A first power source is coupled to the plasma generating element, and a second power source is coupled to the biasing element. A third power source is coupled to the biasing element, wherein the second and third power sources provide a modulated signal to the biasing element.

摘要翻译： 一种用于在晶片处理期间选择性地控制处理室中的等离子体的方法和装置。 该方法包括在要处理的晶片上的室中提供过程气体，以及向等离子体产生元件提供高频RF功率，并将工艺气体点燃到等离子体中。 调制的RF功率耦合到偏置元件，并且根据特定的处理配方执行晶片处理。 该装置包括设置在腔室中并适于支撑晶片的偏置元件和设置在偏置元件和晶片上方的等离子体产生元件。 第一电源耦合到等离子体发生元件，并且第二电源耦合到偏置元件。 第三电源耦合到偏置元件，其中第二和第三电源向偏置元件提供调制信号。

公开(公告)号：US20060175015A1

公开(公告)日：2006-08-10

申请号：US11376430

申请日：2006-03-14

申请人： Jin-Yuan Chen ,  Frank Hooshdaran ,  Dragan Podlesnik

发明人： Jin-Yuan Chen ,  Frank Hooshdaran ,  Dragan Podlesnik

IPC分类号： C23F1/00

CPC分类号： H01J37/321 ,  H01J37/32706

摘要： A method and apparatus for selectively controlling a plasma in a processing chamber during wafer processing. The method includes providing process gasses into the chamber over a wafer to be processed, and providing high frequency RF power to a plasma generating element and igniting the process gases into the plasma. Modulated RF power is coupled to a biasing element, and wafer processing is performed according to a particular processing recipe. The apparatus includes a biasing element disposed in the chamber and adapted to support a wafer, and a plasma generating element disposed over the biasing element and wafer. A first power source is coupled to the plasma generating element, and a second power source is coupled to the biasing element. A third power source is coupled to the biasing element, wherein the second and third power sources provide a modulated signal to the biasing element.

摘要翻译： 一种用于在晶片处理期间选择性地控制处理室中的等离子体的方法和装置。 该方法包括在要处理的晶片上的室中提供过程气体，以及向等离子体产生元件提供高频RF功率，并将工艺气体点燃到等离子体中。 调制的RF功率耦合到偏置元件，并且根据特定的处理配方执行晶片处理。 该装置包括设置在腔室中并适于支撑晶片的偏置元件和设置在偏置元件和晶片上方的等离子体产生元件。 第一电源耦合到等离子体发生元件，并且第二电源耦合到偏置元件。 第三电源耦合到偏置元件，其中第二和第三电源向偏置元件提供调制信号。

公开(公告)号：US08652266B2

公开(公告)日：2014-02-18

申请号：US12212559

申请日：2008-09-17

申请人： Katrina Mikhaylichenko ,  Yizhak Sabba ,  Dragan Podlesnik

发明人： Katrina Mikhaylichenko ,  Yizhak Sabba ,  Dragan Podlesnik

IPC分类号： B08B3/00

CPC分类号： H01L21/67051 ,  H01L21/02071 ,  H01L21/6704 ,  H01L21/67075 ,  H01L21/67253 ,  H01L22/12 ,  H01L22/20

摘要： A system and method for removing polymer residue from around a metal gate structure formed on a surface of a substrate during a post-etch cleaning operation includes determining a plurality of process parameters associated with the metal gate structure and the polymer residue to be removed. A plurality of fabrication layers define the metal gate structure and the process parameters define characteristics of the fabrication layers and the polymer residue. A first cleaning chemistry and second cleaning chemistry are identified and a plurality of application parameters associated with the first and second cleaning chemistries are defined based on the process parameters. The first and second application chemistries are applied sequentially in a controlled manner using the application parameters to substantial remove the polymer residue while preserving the structural integrity of the gate structure.

摘要翻译： 在蚀刻前清洁操作期间从形成在基板的表面上的金属栅极结构周围除去聚合物残留物的系统和方法包括确定与金属栅极结构和待除去的聚合物残余物相关联的多个工艺参数。 多个制造层限定了金属栅极结构，并且工艺参数限定了制造层和聚合物残余物的特性。 识别第一清洁化学品和第二清洁化学品，并且基于过程参数来定义与第一和第二清洁化学品相关联的多个施用参数。 使用应用参数以受控的方式顺序施加第一和第二施用化学物质，以显着除去聚合物残余物，同时保持栅极结构的结构完整性。

公开(公告)号：US06383941B1

公开(公告)日：2002-05-07

申请号：US09611085

申请日：2000-07-06

申请人： Meihua Shen ,  Kenju Nishikido ,  Jeffrey D. Chinn ,  Dragan Podlesnik

发明人： Meihua Shen ,  Kenju Nishikido ,  Jeffrey D. Chinn ,  Dragan Podlesnik

IPC分类号： H01L2100

CPC分类号： H01L21/31138 ,  H01L21/0276 ,  H01L21/3065

摘要： The present disclosure relates to semiconductor processing, and to the plasma etching of organic layers, and in particular antireflective coating layers. We have discovered a particular combination of gases useful in producing chemically reactive plasma species, which provides unexpected control over etched feature critical dimension, etch profile, and uniformity of etch across a substrate surface, despite a difference in the spacing of etched features over the substrate surface. The combination of gases which produces chemically reactive plasma species consists essentially of CxHyFz, a bromine-comprising compound (which is typically HBr), and O2, where x ranges from 1 to 4, y ranges from 0 to 3, and z ranges from 1 to 10. Oxygen atoms may be substituted for hydrogen atoms in the CxHyFz compound to a limited extent Essentially inert gases which do not produce chemically reactive species may be added to the combination of etchant-species producing gases. A combination of CF4/HBr/O2 has been demonstrated to work well. With this combination of plasma source gases, critical Dimension (CD) uniformity control across the surface of the substrate is generally improved by using a volumetric ratio of CxHyFz:HBr ranging from about 2:1 to about 5:1, with a range of about 3:1 to about 4:1 being preferred. An increased plasma density also helps improve CD uniformity control. The volumetric ratio of (CxHyFz+HBr):O2 should range between about 1:1 to 5:1, with a range of about 2:1 to about 3:1 being preferred.

摘要翻译： 本公开涉及半导体处理，以及有机层的等离子体蚀刻，特别是抗反射涂层。 我们已经发现了可用于生产化学反应性等离子体物质的特定气体组合，尽管蚀刻特征在衬底上的间隔有差异，但是它们对蚀刻特征临界尺寸，蚀刻轮廓以及衬底表面上的蚀刻均匀性提供了意想不到的控制 表面。 产生化学反应性等离子体物质的气体的组合基本上由CxHyFz，含溴化合物（通常为HBr）和O 2组成，其中x为1至4，y为0至3，z的范围为1 氧原子可以在有限的程度上代替CxHyFz化合物中的氢原子。基本上不产生化学反应性物质的惰性气体可以添加到产生蚀刻剂的气体组合中。 CF4 / HBr / O2的组合已被证明是有效的。 通过这种等离子体源气体的组合，通常通过使用C 2 H 4 F 5 :H 2 O的体积比约2:1至约5:1的体积比来改善基底表面上的临界尺寸（CD）均匀性控制，其范围为约 优选3:1至约4:1。 增加的等离子体密度也有助于改善CD均匀性控制。 （C x H y F z + HBr）：O 2的体积比应在约1:1至5:1之间，优选约2:1至约3:1的范围。

公开(公告)号：US06380095B1

公开(公告)日：2002-04-30

申请号：US09716074

申请日：2000-11-16

申请人： Wei Liu ,  Yiqiong Wang ,  Maocheng Li ,  Anisul Khan ,  Shaoher Pan ,  Dragan Podlesnik

发明人： Wei Liu ,  Yiqiong Wang ,  Maocheng Li ,  Anisul Khan ,  Shaoher Pan ,  Dragan Podlesnik

IPC分类号： H01L21302

CPC分类号： H01L21/3065

摘要： The present invention pertains to an etch chemistry and method useful for the etching of silicon surfaces. The method is particularly useful in the deep trench etching of silicon where profile control is important. In the case of deep trench etching, at least a portion of the substrate toward the bottom of the trench is etched using a combination of reactive gases including a fluorine-containing compound which does not contain silicon (FC); a silicon-containing compound (SC) which does not contain fluorine; and oxygen (O2).

摘要翻译： 本发明涉及用于蚀刻硅表面的蚀刻化学和方法。 该方法在硅的深沟槽蚀刻中特别有用，其中轮廓控制是重要的。 在深沟槽蚀刻的情况下，使用包含不含硅（FC）的含氟化合物的反应性气体的组合来蚀刻朝向沟槽底部的至少一部分衬底; 不含氟的含硅化合物（SC）; 和氧气（O2）。

公开(公告)号：US06235643B1

公开(公告)日：2001-05-22

申请号：US09371966

申请日：1999-08-10

申请人： David Mui ,  Dragan Podlesnik ,  Wei Liu ,  Gene Lee ,  Nam-Hun Kim ,  Jeff Chinn

发明人： David Mui ,  Dragan Podlesnik ,  Wei Liu ,  Gene Lee ,  Nam-Hun Kim ,  Jeff Chinn

IPC分类号： H01L2100

CPC分类号： H01L21/76232 ,  H01L21/3065 ,  H01L21/3081

摘要： The present invention provides straight forward methods for plasma etching a trench having rounded top corners, or rounded bottom corners, or both in a silicon substrate. A first method for creating a rounded top corner on the etched silicon trench comprises etching both an overlying silicon oxide layer and an upper portion of the silicon substrate during a “break-through” step which immediately precedes the step in which the silicon trench is etched. The plasma feed gas for the break-through step comprises carbon and fluorine. In this method, the photoresist layer used to pattern the etch stack is preferably not removed prior to the break-through etching step. Subsequent to the break-through step, a trench is etched to a desired depth in the silicon substrate using a different plasma feed gas composition. A second method for creating a rounded top corner on the etched silicon trench comprises formation of a built-up extension on the sidewall of an overlying patterned silicon nitride hard mask during etch (break-through) of a silicon oxide adhesion layer which lies between the hard mask and a silicone substrate. The built-up extension upon the silicon nitride sidewall acts as a sacrificial masking material during etch of the silicon trench, delaying etching of the silicon at the outer edges of the top of the trench. This permits completion of trench etching with delayed etching of the top corner of the trench and provides a more gentle rounding (increased radius) at the top corners of the trench. During the etching of the silicon trench to its final dimensions, it is desirable to round the bottom corners of the finished silicon trench. We have discovered that a more rounded bottom trench corner is obtained using a two-step silicon etch process where the second step of the process is carried out at a higher process chamber pressure than the first step.

摘要翻译： 本发明提供了用于在硅衬底中等离子体蚀刻具有圆形顶角或圆形底角或两者的沟槽的直接方法。 用于在蚀刻的硅沟槽上形成圆角顶角的第一种方法包括：在“穿透”步骤​​期间蚀刻覆盖硅氧化物层和硅衬底的上部两者之间，其中硅裂纹之前的步骤 。 用于穿透步骤的等离子体进料气体包括碳和氟。 在该方法中，用于图案化蚀刻叠层的光致抗蚀剂层优选在穿透蚀刻步骤之前不被去除。 在突破步骤之后，使用不同的等离子体进料气体组合物将沟槽蚀刻到硅衬底中的所需深度。 用于在蚀刻的硅沟槽上产生圆角顶角的第二种方法包括在位于第二层之间的氧化硅粘合层的蚀刻（穿透）期间在覆盖的图案化氮化硅硬掩模的侧壁上形成积层延伸。 硬面罩和硅胶基材。 在硅氮化物侧壁上的累积延伸在硅沟槽的蚀刻期间用作牺牲掩模材料，延迟在沟槽顶部的外边缘处的硅的蚀刻。 这允许通过延迟蚀刻沟槽的顶角完成沟槽蚀刻，并且在沟槽的顶角提供更温和的圆化（增加的半径）。 在将硅沟槽蚀刻到其最终尺寸期间，期望圆形完成的硅沟槽的底角。 我们已经发现，使用两步硅蚀刻工艺获得更圆的底部沟槽角，其中该工艺的第二步骤在比第一步高的处理室压力下进行。

公开(公告)号：US20100229890A1

公开(公告)日：2010-09-16

申请号：US12401590

申请日：2009-03-10

申请人： Yizhak T. Sabba ,  Seokmin Yun ,  Mark Kawaguchi ,  Mark Wilcoxson ,  Dragan Podlesnik

发明人： Yizhak T. Sabba ,  Seokmin Yun ,  Mark Kawaguchi ,  Mark Wilcoxson ,  Dragan Podlesnik

IPC分类号： B08B3/00 ,  B08B7/00

CPC分类号： H01L21/02057 ,  H01L21/67051

摘要： Apparatus and methods for removing particle contaminants from a surface of a substrate includes coating a layer of a viscoelastic material on the surface. The viscoelastic material is coated as a thin film and exhibits substantial liquid-like characteristic. An external force is applied to a first area of the surface coated with the viscoelastic material such that a second area of the surface coated with the viscoelastic material is not substantially subjected to the applied force. The force is applied for a time duration that is shorter than a intrinsic time of the viscoelastic material so as to access solid-like characteristic of the viscoelastic material. The viscoelastic material exhibiting solid-like characteristic interacts at least partially with at least some of the particle contaminants present on the surface. The viscoelastic material along with at least some of the particle contaminants is removed from the first area of the surface while the viscoelastic material is exhibiting solid-like characteristics.

摘要翻译： 从基材表面去除颗粒污染物的设备和方法包括在表面上涂覆一层粘弹性材料。 粘弹性材料被涂覆为薄膜并呈现出显着的液体特性。 外力施加到涂覆有粘弹性材料的表面的第一区域，使得涂覆有粘弹性材料的表面的第二区域基本上不受施加的力。 施加力比粘弹性材料的固有时间短的持续时间，以获得粘弹性材料的固体特性。 具有固体样特性的粘弹性材料至少部分地与存在于表面上的至少一些颗粒污染物相互作用。 粘弹性材料与至少一些颗粒污染物一起从表面的第一区域去除，而粘弹性材料呈现出固体状特征。

公开(公告)号：US20090156452A1

公开(公告)日：2009-06-18

申请号：US12131654

申请日：2008-06-02

申请人： David S.L. Mui ,  Satish Srinivasan ,  Grant Peng ,  Ji Zhu ,  Shih-Chung Kon ,  Dragan Podlesnik ,  Arjun Mendiratta

发明人： David S.L. Mui ,  Satish Srinivasan ,  Grant Peng ,  Ji Zhu ,  Shih-Chung Kon ,  Dragan Podlesnik ,  Arjun Mendiratta

IPC分类号： C11D3/37

CPC分类号： C11D7/5009 ,  C11D3/3723 ,  C11D3/3765 ,  C11D3/3773 ,  C11D7/261 ,  C11D7/3263 ,  C11D7/34 ,  C11D11/0047 ,  H01L21/02057 ,  H01L21/67051 ,  Y10S134/902

摘要： The embodiments of the present invention provide improved materials for cleaning patterned substrates with fine features. The cleaning materials have advantages in cleaning patterned substrates with fine features without substantially damaging the features. The cleaning materials are fluid, either in liquid phase, or in liquid/gas phase, and deform around device features; therefore, the cleaning materials do not substantially damage the device features or reduce damage all together. The cleaning materials containing polymers of a polymeric compound with large molecular weight capture the contaminants on the substrate. In addition, the cleaning materials entrap the contaminants and do not return the contaminants to the substrate surface. The polymers of one or more polymeric compounds with large molecular weight form long polymer chains, which can also be cross-linked to form a network (or polymeric network). The long polymer chains and/or polymer network show superior capabilities of capturing and entrapping contaminants, in comparison to conventional cleaning materials.

摘要翻译： 本发明的实施例提供用于清洁具有精细特征的图案化衬底的改进材料。 清洁材料在清洁具有精细特征的图案化基材上具有优点，而基本上不损坏特征。 清洁材料是流体，液相或液相/气相，并围绕装置特征变形; 因此，清洁材料基本上不会损坏设备特征或将损坏降低在一起。 包含具有大分子量的聚合物的聚合物的清洁材料捕获基底上的污染物。 此外，清洁材料夹带污染物并且不会将污染物返回到基底表面。 一种或多种具有大分子量的聚合物的聚合物形成长的聚合物链，其也可以交联以形成网络（或聚合物网络）。 与传统清洁材料相比，长的聚合物链和/或聚合物网络显示出捕获和捕获污染物的优异性能。

公开(公告)号：US06808647B1

公开(公告)日：2004-10-26

申请号：US09352008

申请日：1999-07-12

申请人： Songlin Xu ,  Zhiwen Sun ,  Dragan Podlesnik ,  Xueyu Qian

发明人： Songlin Xu ,  Zhiwen Sun ,  Dragan Podlesnik ,  Xueyu Qian

IPC分类号： B44C122

CPC分类号： H01J37/32431 ,  H01J2237/022 ,  H01L21/3065 ,  H01L21/32137

摘要： A method and apparatus for reducing the sensitivity of semiconductor processing to chamber conditions is provided. Process repeatability of common processes are affected by changing surface conditions which alter the recombination rates of processing chemicals to the chamber surfaces. In one aspect of the invention, a composition of one or more etchants is selected to optimize the etch performance and reduce deposition on chamber surfaces. The one or more etchants are selected to minimize buildup on the chamber surfaces, thereby controlling the chamber surface condition to minimize changes in etch rates due to differing recombination rates of free radicals with different surface conditions and achieve etch repeatability. In another embodiment, the etchant chemistry is adjusted to reduce the change to internal surface conditions after a cleaning cycle. In another embodiment, a process recipe is selected to reduce the sensitivity of the etch process to the chamber conditions. In another embodiment, chamber surface materials are selected to minimize the differences in recombination rates of free radicals on the surface materials and the byproduct depositions formed on the materials during processing.

摘要翻译： 提供了一种用于降低半导体加工对腔室条件的灵敏度的方法和装置。 常规工艺的工艺重复性受到改变表面条件的影响，这些表面条件改变了处理化学品与室表面的复合速率。 在本发明的一个方面，选择一种或多种蚀刻剂的组合物以优化蚀刻性能并减少在室表面上的沉积。 选择一种或多种蚀刻剂以最小化室表面上的积聚，由此由于由于具有不同表面条件的自由基的不同重组速率而导致的蚀刻速率的变化最小化并实现蚀刻可重复性，从而控制室表面状态。 在另一个实施方案中，调整蚀刻剂化学性以在清洁循环之后减少对内表面状况的变化。 在另一个实施例中，选择工艺配方以降低蚀刻工艺对腔室条件的灵敏度。 在另一个实施方案中，选择室表面材料以最小化表面材料上的自由基和在处理期间在材料上形成的副产物沉积物的复合速率的差异。

公开(公告)号：US06518192B2

公开(公告)日：2003-02-11

申请号：US10013115

申请日：2001-12-07

申请人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

发明人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

IPC分类号： H01L2100

CPC分类号： H01L21/30655 ,  B81B2203/033 ,  B81C1/00571 ,  B81C2201/0132 ,  H01L21/3065 ,  H01L21/32137

摘要： A two-step etch method for etching a masked layer or layers that include fast and slow etching regions is described. Fast and slow etching regions may arise in a variety of devices, such as microelectrical mechanical system (“MEMS”) applications and mixed signal (i.e. analog and digital) integrated circuits, as well as other integrated circuits and devices. In one embodiment, a first etchant is used to etch through the layer in the fastest etching region, and then a second etchant is used to complete etching through the layer in the slowest etching region.