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    PITCH REDUCED PATTERNS RELATIVE TO PHOTOLITHOGRAPHY FEATURES
    1.
    发明申请
    PITCH REDUCED PATTERNS RELATIVE TO PHOTOLITHOGRAPHY FEATURES 失效
    相对于光刻特征的PITCH减少图案

    公开(公告)号：US20070161251A1

    公开(公告)日：2007-07-12

    申请号：US11681027

    申请日：2007-03-01

    申请人： Luan Tran ,  William Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer Abatchev ,  Gurtej Sandhu ,  D. Durcan

    发明人： Luan Tran ,  William Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer Abatchev ,  Gurtej Sandhu ,  D. Durcan

    IPC分类号： H01L21/302

    CPC分类号： H01L21/0338 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3088

    摘要： Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.

    摘要翻译： 通过使用通过组合两个单独形成的图案形成的掩模蚀刻衬底来形成集成电路的不同尺寸的特征。 间距乘法用于形成第一图案的相对较小的特征以及用于形成第二图案的较大特征的常规光刻。 间距倍增通过对光致抗蚀剂进行图案化，然后将该图案蚀刻成无定形碳层来实现。 然后在无定形碳的侧壁上形成侧壁间隔物。 去除无定形碳，留下限定第一掩模图案的侧壁间隔物。 然后将底部抗反射涂层（BARC）沉积在间隔物周围以形成平坦表面，并且在BARC上形成光致抗蚀剂层。 接下来通过常规光刻法将光致抗蚀剂图案化以形成第二图案，然后将其转印到BARC。 通过第一图案和第二图案形成的组合图案被转印到下面的非晶硅层，并且图案经受碳带以去除BARC和光致抗蚀剂材料。 然后将组合图案转移到氧化硅层，然后转移到无定形碳掩模层。 具有不同尺寸特征的组合掩模图案然后通过无定形碳硬掩模层蚀刻到下面的衬底中。

    Multiple deposition for integration of spacers in pitch multiplication process
    3.
    发明申请
    Multiple deposition for integration of spacers in pitch multiplication process 有权
    用于在间距乘法过程中整合间隔物的多次沉积

    公开(公告)号：US20070049040A1

    公开(公告)日：2007-03-01

    申请号：US11213486

    申请日：2005-08-25

    申请人： Jingyi Bai ,  Gurtej Sandhu ,  Shuang Meng

    发明人： Jingyi Bai ,  Gurtej Sandhu ,  Shuang Meng

    IPC分类号： C23F1/00 ,  H01L21/311 ,  H01L21/302 ,  B44C1/22

    CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088

    摘要： Pitch multiplication is performed using a two step process to deposit spacer material on mandrels. The precursors of the first step react minimally with the mandrels, forming a barrier layer against chemical reactions for the deposition process of the second step, which uses precursors more reactive with the mandrels. Where the mandrels are formed of amorphous carbon and the spacer material is silicon oxide, the silicon oxide is first deposited by a plasma enhanced deposition process and then by a thermal chemical vapor deposition process. Oxygen gas and plasma-enhanced tetraethylorthosilicate (TEOS) are used as reactants in the plasma enhanced process, while ozone and TEOS are used as reactants in the thermal chemical vapor deposition process. The oxygen gas is less reactive with the amorphous carbon than ozone, thereby minimizing deformation of the mandrels caused by oxidation of the amorphous carbon.

    摘要翻译： 使用两步法将间隔物材料沉积在心轴上进行间距倍增。 第一步的前体与心轴发生最小的反应，形成抵抗第二步骤沉积过程的化学反应的阻挡层，其使用与心轴更具反应性的前体。 在心轴由非晶碳形成并且间隔物材料是氧化硅的情况下，首先通过等离子体增强沉积工艺沉积氧化硅，然后通过热化学气相沉积工艺沉积。 在等离子体增强过程中使用氧气和等离子体增强的四乙基原硅酸盐（TEOS）作为反应物，而在热化学气相沉积工艺中使用臭氧和TEOS作为反应物。 氧气与无定形碳的反应性低于臭氧，从而最小化由无定形碳的氧化引起的心轴的变形。

    MULTIPLE DEPOSITION FOR INTEGRATION OF SPACERS IN PITCH MULTIPLICATION PROCESS
    4.
    发明申请
    MULTIPLE DEPOSITION FOR INTEGRATION OF SPACERS IN PITCH MULTIPLICATION PROCESS 有权
    用于集成多个过程中的间隔的多个沉积

    公开(公告)号：US20070117310A1

    公开(公告)日：2007-05-24

    申请号：US11625165

    申请日：2007-01-19

    申请人： Jingyi Bai ,  Gurtej Sandhu ,  Shuang Meng

    发明人： Jingyi Bai ,  Gurtej Sandhu ,  Shuang Meng

    IPC分类号： H01L21/8242

    CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088

    摘要： Pitch multiplication is performed using a two step process to deposit spacer material on mandrels. The precursors of the first step react minimally with the mandrels, forming a barrier layer against chemical reactions for the deposition process of the second step, which uses precursors more reactive with the mandrels. Where the mandrels are formed of amorphous carbon and the spacer material is silicon oxide, the silicon oxide is first deposited by a plasma enhanced deposition process and then by a thermal chemical vapor deposition process. Oxygen gas and plasma-enhanced tetraethylorthosilicate (TEOS) are used as reactants in the plasma enhanced process, while ozone and TEOS are used as reactants in the thermal chemical vapor deposition process. The oxygen gas is less reactive with the amorphous carbon than ozone, thereby minimizing deformation of the mandrels caused by oxidation of the amorphous carbon.

    摘要翻译： 使用两步法将间隔物材料沉积在心轴上进行间距倍增。 第一步的前体与心轴发生最小的反应，形成抵抗第二步骤沉积过程的化学反应的阻挡层，其使用与心轴更具反应性的前体。 在心轴由非晶碳形成并且间隔物材料是氧化硅的情况下，首先通过等离子体增强沉积工艺沉积氧化硅，然后通过热化学气相沉积工艺沉积。 在等离子体增强过程中使用氧气和等离子体增强的四乙基原硅酸盐（TEOS）作为反应物，而在热化学气相沉积工艺中使用臭氧和TEOS作为反应物。 氧气与无定形碳的反应性低于臭氧，从而最小化由无定形碳的氧化引起的心轴的变形。

    Method to reduce charge buildup during high aspect ratio contact etch
    5.
    发明申请
    Method to reduce charge buildup during high aspect ratio contact etch 有权
    在高纵横比接触蚀刻期间减少电荷积累的方法

    公开(公告)号：US20070049018A1

    公开(公告)日：2007-03-01

    申请号：US11213283

    申请日：2005-08-26

    申请人： Gurtej Sandhu ,  Max Hineman ,  Daniel Steckert ,  Jingyi Bai ,  Shane Trapp ,  Tony Schrock

    发明人： Gurtej Sandhu ,  Max Hineman ,  Daniel Steckert ,  Jingyi Bai ,  Shane Trapp ,  Tony Schrock

    IPC分类号： H01L21/44 ,  H01L21/302

    CPC分类号： H01L21/76802 ,  H01L21/31116 ,  Y10S438/906

    摘要： A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A plasma etching gas is formed from a carbon source gas. Dopants are mixed into the gas. The doped plasma etching gas etches a substantially vertical contact hole through the oxide layer by doping carbon chain polymers formed along the sidewalls of the contact holes during the etching process into a conductive state. The conductive state of the carbon chain polymers reduces the charge buildup along sidewalls to prevent twisting of the contact holes by bleeding off the charge and ensuring proper alignment with active area landing regions. The etching stops at the underlying substrate.

    摘要翻译： 描述了使用硬光致抗蚀剂掩模的高纵横比接触蚀刻氧化物层中的基本上垂直的接触孔的方法。 氧化物层沉积在下面的衬底上。 由碳源气体形成等离子体蚀刻气体。 掺杂剂混入气体中。 掺杂的等离子体蚀刻气体通过在蚀刻工艺期间将沿着接触孔的侧壁形成的碳链聚合物掺杂到导电状态来蚀刻通过氧化物层的基本垂直的接触孔。 碳链聚合物的导电状态减少了沿着侧壁的电荷累积，以防止通过渗出电荷并确保与有源区着陆区域的适当对准来接合孔的扭曲。 蚀刻停止在下面的基底。

    Pitch reduced patterns relative to photolithography features
    6.
    发明申请
    Pitch reduced patterns relative to photolithography features 有权
    相对于光刻特征的间距减小

    公开(公告)号：US20060211260A1

    公开(公告)日：2006-09-21

    申请号：US11214544

    申请日：2005-08-29

    申请人： Luan Tran ,  William Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi (Jenny) Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer Abatchev ,  Gurtej Sandhu ,  D. Durcan

    发明人： Luan Tran ,  William Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi (Jenny) Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer Abatchev ,  Gurtej Sandhu ,  D. Durcan

    IPC分类号： H01L21/31

    CPC分类号： H01L21/0338 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3088

    摘要： Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.

    摘要翻译： 通过使用通过组合两个单独形成的图案形成的掩模蚀刻衬底来形成集成电路的不同尺寸的特征。 间距乘法用于形成第一图案的相对较小的特征以及用于形成第二图案的较大特征的常规光刻。 间距倍增通过对光致抗蚀剂进行图案化，然后将该图案蚀刻成无定形碳层来实现。 然后在无定形碳的侧壁上形成侧壁间隔物。 去除无定形碳，留下限定第一掩模图案的侧壁间隔物。 然后将底部抗反射涂层（BARC）沉积在间隔物周围以形成平坦表面，并且在BARC上形成光致抗蚀剂层。 接下来通过常规光刻法将光致抗蚀剂图案化以形成第二图案，然后将其转印到BARC。 通过第一图案和第二图案形成的组合图案被转印到下面的非晶硅层，并且图案经受碳带以去除BARC和光致抗蚀剂材料。 然后将组合图案转移到氧化硅层，然后转移到无定形碳掩模层。 具有不同尺寸特征的组合掩模图案然后通过无定形碳硬掩模层蚀刻到下面的衬底中。

    Pitch multiplication using self-assembling materials
    8.
    发明授权
    Pitch multiplication using self-assembling materials 有权

    公开(公告)号：US10515801B2

    公开(公告)日：2019-12-24

    申请号：US12908206

    申请日：2010-10-20

    申请人： Gurtej Sandhu

    发明人： Gurtej Sandhu

    IPC分类号： H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213

    摘要： Self-assembling materials, such as block copolymers, are used as mandrels for pitch multiplication. The copolymers are deposited over a substrate and directed to self-assemble into a desired pattern. One of the blocks forming the block copolymers is selectively removed. The remaining blocks are used as mandrels for pitch multiplication. Spacer material is blanket deposited over the blocks. The spacer material is subjected to a spacer etch to form spacers on sidewalls of the mandrels. The mandrels are selectively removed to leave free-standing spacers. The spacers may be used as pitch-multiplied mask features to define a pattern in an underlying substrate.

    Self-aligned nano-structures
    10.
    发明授权
    Self-aligned nano-structures 有权
    自对准纳米结构

    公开(公告)号：US08946907B2

    公开(公告)日：2015-02-03

    申请号：US13526225

    申请日：2012-06-18

    申请人： Gurtej Sandhu

    发明人： Gurtej Sandhu

    IPC分类号： H01L23/52 ,  H01L21/311 ,  H01L21/033

    CPC分类号： H01L23/5226 ,  H01L21/0337 ,  H01L21/31144 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for creating structures in a semiconductor assembly is provided. The method includes etching apertures into a dielectric layer and applying a polymer layer over the dielectric layer. The polymer layer is applied uniformly and fills the apertures at different rates depending on the geometry of the apertures, or on the presence or absence of growth accelerating material. The polymer creates spacers for the etching of additional structure in between the spacers. The method is capable of achieving structures smaller than current lithography techniques.

    摘要翻译： 提供了一种用于在半导体组件中产生结构的方法。 该方法包括将孔蚀刻到电介质层中，并在该介电层上施加聚合物层。 均匀地施加聚合物层，并根据孔的几何形状，或者存在或不存在生长促进材料，以不同的速率填充孔。 该聚合物产生用于蚀刻间隔物之间​​的附加结构的间隔物。 该方法能够实现比当前光刻技术更小的结构。