公开(公告)号：US10396229B2

公开(公告)日：2019-08-27

申请号：US13103583

申请日：2011-05-09

申请人： Joel P. De Souza ,  Harold J. Hovel ,  Daniel A. Inns ,  Jeehwan Kim ,  Christian Lavoie ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Davood Shahrjerdi ,  Zhen Zhang

发明人： Joel P. De Souza ,  Harold J. Hovel ,  Daniel A. Inns ,  Jeehwan Kim ,  Christian Lavoie ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Davood Shahrjerdi ,  Zhen Zhang

IPC分类号： H01L31/07 ,  H01L31/0224 ,  H01L31/18 ,  H01L31/068

摘要： A solar cell having n-type and p-type interdigitated back contacts (IBCs), which cover the entire back surface of the absorber layer. The spatial separation of the IBCs is in a direction perpendicular to the back surface, thus providing borderless contacts having a zero-footprint separation. As the contacts are on the back, photons incident on the cell's front surface can be absorbed without any shadowing.

公开(公告)号：US20120285518A1

公开(公告)日：2012-11-15

申请号：US13103583

申请日：2011-05-09

申请人： Joel P. De Souza ,  Harold John Hovel ,  Daniel Inns ,  Jeehwan Kim ,  Christian Lavoie ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Davood Shahrjerdi ,  Zhen Zhang

发明人： Joel P. De Souza ,  Harold John Hovel ,  Daniel Inns ,  Jeehwan Kim ,  Christian Lavoie ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Davood Shahrjerdi ,  Zhen Zhang

IPC分类号： H01L31/06 ,  H01L31/18

CPC分类号： H01L31/0682 ,  H01L31/022441 ,  H01L31/07 ,  H01L31/1804 ,  H01L31/1864 ,  Y02E10/547 ,  Y02P70/521

摘要： A solar cell having n-type and p-type interdigitated back contacts (IBCs), which cover the entire back surface of the absorber layer. The spatial separation of the IBCs is in a direction perpendicular to the back surface, thus providing borderless contacts having a zero-footprint separation. As the contacts are on the back, photons incident on the cell's front surface can be absorbed without any shadowing.

摘要翻译： 一种太阳能电池，其具有覆盖吸收层的整个后表面的n型和p型交叉指接头（IBC）。 IBC的空间分离是在垂直于后表面的方向上，从而提供具有零占位分隔的无边界接触。 随着触点在背面，入射在电池前表面的光子可以被吸收而不会有任何阴影。

公开(公告)号：US20120285517A1

公开(公告)日：2012-11-15

申请号：US13103490

申请日：2011-05-09

申请人： Joel P. de Souza ,  Harold John Hovel ,  Daniel Inns ,  Jeehwan Kim ,  Christian Lavoie ,  Conal Eugene Murray ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Ghavam Shahidi ,  Davood Shahrjerdi ,  Zhen Zhang

发明人： Joel P. de Souza ,  Harold John Hovel ,  Daniel Inns ,  Jeehwan Kim ,  Christian Lavoie ,  Conal Eugene Murray ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Ghavam Shahidi ,  Davood Shahrjerdi ,  Zhen Zhang

IPC分类号： H01L31/108 ,  H01L31/18

CPC分类号： H01L31/07 ,  H01L31/0321 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： A Schottky Barrier solar cell having at least one of a low work function region and a high work function region provided on the front or back surface of a lightly-doped absorber material, which may be produced in a variety of different geometries. The method of producing the Schottky Barrier solar cells allows for short processing times and the use of low temperatures.

摘要翻译： 一种肖特基势垒太阳能电池，其具有设置在轻掺杂的吸收材料的前表面或后表面上的低功函数区域和高功函数区域中的至少一个，其可以以各种不同的几何形状生产。 生产肖特基势垒太阳能电池的方法允许短的处理时间和低温的使用。

公开(公告)号：US20130200443A1

公开(公告)日：2013-08-08

申请号：US13368750

申请日：2012-02-08

申请人： Christian Lavoie ,  Uzma Rana ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Paul Michael Solomon ,  Yanning Sun ,  Zhen Zhang

发明人： Christian Lavoie ,  Uzma Rana ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Paul Michael Solomon ,  Yanning Sun ,  Zhen Zhang

IPC分类号： H01L29/78 ,  H01L23/48 ,  H01L21/336 ,  H01L21/22

CPC分类号： H01L21/2258 ,  H01L21/28575 ,  H01L29/20 ,  H01L29/41783 ,  H01L29/452 ,  H01L29/66522 ,  H01L2924/0002 ,  H01L2924/00

摘要： Techniques for fabricating self-aligned contacts in III-V FET devices are provided. In one aspect, a method for fabricating a self-aligned contact to III-V materials includes the following steps. At least one metal is deposited on a surface of the III-V material. The at least one metal is reacted with an upper portion of the III-V material to form a metal-III-V alloy layer which is the self-aligned contact. An etch is used to remove any unreacted portions of the at least one metal. At least one impurity is implanted into the metal-III-V alloy layer. The at least one impurity implanted into the metal-III-V alloy layer is diffused to an interface between the metal-III-V alloy layer and the III-V material thereunder to reduce a contact resistance of the self-aligned contact.

摘要翻译： 提供了在III-V FET器件中制造自对准触点的技术。 一方面，用于制造与III-V材料的自对准接触的方法包括以下步骤。 在III-V材料的表面上沉积至少一种金属。 所述至少一种金属与III-V材料的上部反应形成作为自对准接触的金属III-V合金层。 蚀刻用于去除至少一种金属的任何未反应部分。 将至少一种杂质注入到金属III-V合金层中。 注入到金属III-V合金层中的至少一种杂质扩散到金属III-V合金层与其之间的III-V材料之间的界面，以降低自对准接触的接触电阻。

公开(公告)号：US09105571B2

公开(公告)日：2015-08-11

申请号：US13368750

申请日：2012-02-08

申请人： Christian Lavoie ,  Uzma Rana ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Paul Michael Solomon ,  Yanning Sun ,  Zhen Zhang

发明人： Christian Lavoie ,  Uzma Rana ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Paul Michael Solomon ,  Yanning Sun ,  Zhen Zhang

IPC分类号： H01L21/24 ,  H01L21/225 ,  H01L21/285 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/20

CPC分类号： H01L21/2258 ,  H01L21/28575 ,  H01L29/20 ,  H01L29/41783 ,  H01L29/452 ,  H01L29/66522 ,  H01L2924/0002 ,  H01L2924/00

摘要： Techniques for fabricating self-aligned contacts in III-V FET devices are provided. In one aspect, a method for fabricating a self-aligned contact to III-V materials includes the following steps. At least one metal is deposited on a surface of the III-V material. The at least one metal is reacted with an upper portion of the III-V material to form a metal-III-V alloy layer which is the self-aligned contact. An etch is used to remove any unreacted portions of the at least one metal. At least one impurity is implanted into the metal-III-V alloy layer. The at least one impurity implanted into the metal-III-V alloy layer is diffused to an interface between the metal-III-V alloy layer and the III-V material thereunder to reduce a contact resistance of the self-aligned contact.

摘要翻译： 提供了在III-V FET器件中制造自对准触点的技术。 一方面，用于制造与III-V材料的自对准接触的方法包括以下步骤。 在III-V材料的表面上沉积至少一种金属。 所述至少一种金属与III-V材料的上部反应形成作为自对准接触的金属III-V合金层。 蚀刻用于去除至少一种金属的任何未反应部分。 将至少一种杂质注入到金属III-V合金层中。 注入到金属III-V合金层中的至少一种杂质扩散到金属III-V合金层与其之间的III-V材料之间的界面，以降低自对准接触的接触电阻。

公开(公告)号：US08889537B2

公开(公告)日：2014-11-18

申请号：US12833272

申请日：2010-07-09

申请人： Cryil Cabral, Jr. ,  John M. Cotte ,  Dinesh R. Koli ,  Laura L. Kosbar ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Stephen M. Rossnagel ,  Zhen Zhang

发明人： Cryil Cabral, Jr. ,  John M. Cotte ,  Dinesh R. Koli ,  Laura L. Kosbar ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Stephen M. Rossnagel ,  Zhen Zhang

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L29/45

CPC分类号： H01L21/28512 ,  H01L21/28518 ,  H01L29/456

摘要： A method for formation of a segregated interfacial dopant layer at a junction between a semiconductor material and a silicide layer includes depositing a doped metal layer over the semiconductor material; annealing the doped metal layer and the semiconductor material, wherein the anneal causes a portion of the doped metal layer and a portion of the semiconductor material to react to form the silicide layer on the semiconductor material, and wherein the anneal further causes the segregated interfacial dopant layer to form between the semiconductor material and the silicide layer, the segregated interfacial dopant layer comprising dopants from the doped metal layer; and removing an unreacted portion of the doped metal layer from the silicide layer.

摘要翻译： 在半导体材料和硅化物层之间的结处形成分离的界面掺杂剂层的方法包括在半导体材料上沉积掺杂的金属层; 退火所述掺杂金属层和所述半导体材料，其中所述退火使所述掺杂金属层的一部分和所述半导体材料的一部分反应以在所述半导体材料上形成所述硅化物层，并且其中所述退火还导致所述分离的界面掺杂剂 层，以形成在半导体材料和硅化物层之间，分离的界面掺杂剂层包含来自掺杂金属层的掺杂剂; 以及从所述硅化物层去除所述掺杂金属层的未反应部分。

公开(公告)号：US08859316B2

公开(公告)日：2014-10-14

申请号：US12825527

申请日：2010-06-29

申请人： Dechao Guo ,  Christian Lavoie ,  Christine Ouyang Qiqing ,  Yanning Sun ,  Zhen Zhang

发明人： Dechao Guo ,  Christian Lavoie ,  Christine Ouyang Qiqing ,  Yanning Sun ,  Zhen Zhang

IPC分类号： H01L21/00 ,  H01L29/06 ,  G01N27/414

CPC分类号： G01N27/4145 ,  G01N27/4146 ,  H01L29/0673

摘要： A Schottky junction silicon nanowire field-effect biosensor/molecule detector with a nanowire thickness of 10 nanometer or less and an aligned source/drain workfunction for increased sensitivity. The nanowire channel is coated with a surface treatment to which a molecule of interest absorbs, which modulates the conductivity of the channel between the Schottky junctions sufficiently to qualitatively and quantitatively measure the presence and amount of the molecule.

摘要翻译： 肖特基结的硅纳米线场效应生物传感器/分子检测器，纳米线厚度为10纳米或更小，并具有对准的源极/漏极功能，以提高灵敏度。 纳米线通道涂覆有目标分子吸收的表面处理，其可以充分调节肖特基结之间的通道的电导率以定性和定量地测量分子的存在和量。

公开(公告)号：US08741753B2

公开(公告)日：2014-06-03

申请号：US13611736

申请日：2012-09-12

申请人： Kisik Choi ,  Christian Lavoie ,  Paul M. Solomon ,  Bin Yang ,  Zhen Zhang

发明人： Kisik Choi ,  Christian Lavoie ,  Paul M. Solomon ,  Bin Yang ,  Zhen Zhang

IPC分类号： H01L21/20 ,  H01L21/3205 ,  H01L21/00

CPC分类号： H01L29/7833 ,  H01L21/28512 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545

摘要： A device includes a gate stack formed over a channel in a semiconductor substrate. The gate stack includes a layer of gate insulator material, a layer of gate metal overlying the layer of gate insulator material, and a layer of contact metal overlying the layer band edge gate metal. The device further includes source and drain contacts adjacent to the channel. The source and drain contacts each include a layer of the gate metal that overlies and is in direct electrical contact with a doped region of the semiconductor substrate, and a layer of contact metal that overlies the layer of gate metal.

摘要翻译： 一种器件包括形成在半导体衬底中的沟道上方的栅叠层。 栅极堆叠包括栅极绝缘体材料层，覆盖栅极绝缘体材料层的栅极金属层和覆盖层带边缘栅极金属的接触金属层。 该装置还包括邻近通道的源极和漏极接触。 源极和漏极触点各自包括覆盖并与半导体衬底的掺杂区域直接电接触的栅极金属层以及覆盖在栅极金属层上的接触金属层。

公开(公告)号：US08456011B2

公开(公告)日：2013-06-04

申请号：US13006664

申请日：2011-01-14

申请人： Christian Lavoie ,  Ahmet S. Ozcan ,  Zhen Zhang ,  Bin Yang

发明人： Christian Lavoie ,  Ahmet S. Ozcan ,  Zhen Zhang ,  Bin Yang

IPC分类号： H01L23/532

CPC分类号： H01L21/768 ,  H01L21/28518 ,  H01L23/485 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/66575 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a metal semiconductor alloy that includes forming an intermixed metal semiconductor region to a first depth of a semiconductor substrate without thermal diffusion. The intermixed metal semiconductor region is annealed to form a textured metal semiconductor alloy. A second metal layer is formed on the textured metal semiconductor alloy. The second metal layer on the textured metal semiconductor alloy is then annealed to form a metal semiconductor alloy contact, in which metal elements from the second metal layer are diffused through the textured metal semiconductor alloy to provide a templated metal semiconductor alloy. The templated metal semiconductor alloy includes a grain size that is greater than 2× for the metal semiconductor alloy, which has a thickness ranging from 15 nm to 50 nm.

公开(公告)号：US08278200B2

公开(公告)日：2012-10-02

申请号：US13012043

申请日：2011-01-24

申请人： Christian Lavoie ,  Tak H. Ning ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

发明人： Christian Lavoie ,  Tak H. Ning ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

IPC分类号： H01L21/20

CPC分类号： H01L21/28518

摘要： In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure.

摘要翻译： 在一个示例性实施例中，一种可由机器读取的程序存储设备，其有形地体现了可由机器执行的用于执行操作的指令程序，所述操作包括：在半导体结构的表面上沉积具有第一金属的第一层， 第一层在第一层和半导体结构的界面处形成第一混合区; 去除沉积的第一层的一部分以暴露第一混合区; 在所述第一混合区域上沉积具有第二金属的第二层，其中沉积所述第二层在所述第二层和所述第一混合区的界面处产生第二混合区; 去除沉积的第二层的一部分以暴露第二混合区; 以及在所述半导体结构上执行至少一个退火。