公开(公告)号：US08242007B2

公开(公告)日：2012-08-14

申请号：US12401693

申请日：2009-03-11

申请人： Jong-ho Park ,  Chang-ki Jeon ,  Hyi-jeong Park

发明人： Jong-ho Park ,  Chang-ki Jeon ,  Hyi-jeong Park

IPC分类号： H01L27/06 ,  H01L21/60

CPC分类号： H01L21/8249 ,  H01L21/2256 ,  H01L21/823814 ,  H01L27/0623

摘要： Provided are a semiconductor device including a source/drain and a gate formed using a doped polysilicon process, and a method of fabricating the semiconductor device. The method comprises: forming a gate insulating layer on a part of an active region on a first conductivity type epitaxial layer; forming a conductive layer on the epitaxial layer; implanting high concentration impurities of a second conductivity type a first portion of the conductive layer on the gate insulating layer and second portions of the conductive layer on both sides of the first insulating layer; patterning the conductive layer; forming a second insulating layer on the epitaxial layer and high concentration impurity regions of the second conductivity type below the second conductive pattern; and implanting low-concentration impurities of the second conductivity type into the epitaxial layer between a gate structure and the high concentration impurity regions.

摘要翻译： 提供了包括使用掺杂多晶硅工艺形成的源极/漏极和栅极的半导体器件，以及制造半导体器件的方法。 该方法包括：在第一导电型外延层的有源区的一部分上形成栅极绝缘层; 在外延层上形成导电层; 将第二导电类型的高浓度杂质注入到第一绝缘层的栅绝缘层上的导电层的第一部分和导电层的第二部分上; 图案化导电层; 在所述外延层上形成第二绝缘层，在所述第二导电图案之下形成所述第二导电类型的高浓度杂质区; 以及将第二导电类型的低浓度杂质注入到栅极结构和高浓度杂质区之间的外延层中。

公开(公告)号：US20100320537A1

公开(公告)日：2010-12-23

申请号：US12870913

申请日：2010-08-30

申请人： Jong-ho Park ,  Chang-ki Jeon ,  Hyi-Jeong Park ,  Hye-mi Kim

发明人： Jong-ho Park ,  Chang-ki Jeon ,  Hyi-Jeong Park ,  Hye-mi Kim

IPC分类号： H01L27/06 ,  H01L29/78

CPC分类号： H01L21/8249 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7809 ,  H01L29/7812

摘要： Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device using a DMOS device includes: a semiconductor substrate, in which a first conductive type well is formed; a first conductive type gate electrode formed on the semiconductor substrate with a gate insulating layer intervening between the gate electrode and the semiconductor substrate; a second conductive type body electrode formed on the semiconductor substrate and separated from the gate electrode; a first conductive type drain electrode formed on the semiconductor substrate and separated from the gate electrode and the body electrode; a second conductive type first body region formed in the well under the body electrode; a second conductive type second body region extending from the first body region to the gate insulating layer and formed in the well; a first conductive type source region formed in the second body region and extending from the first body region to the gate insulating layer; and a first conductive type source electrode extending from the source region to surround the gate electrode on the semiconductor substrate with an insulating layer intervening between the source electrode and gate electrode.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 使用DMOS器件的半导体器件包括：形成第一导电型阱的半导体衬底; 形成在所述半导体衬底上的第一导电型栅极电极，所述栅极绝缘层介于所述栅电极和所述半导体衬底之间; 形成在所述半导体基板上并与所述栅电极分离的第二导电型体电极; 形成在所述半导体基板上并与所述栅电极和所述主体电极分离的第一导电型漏电极; 形成在所述体电极下方的所述阱内的第二导电型第一体区域; 第二导电类型的第二主体区域，其从所述第一主体区域延伸到所述栅极绝缘层并形成在所述阱中; 形成在所述第二主体区域中并从所述第一主体区域延伸到所述栅极绝缘层的第一导电型源极区域; 以及第一导电型源电极，其从所述源极区域延伸，以在所述半导体衬底上围绕所述栅极电极，所述绝缘层介于所述源电极和栅电极之间。

公开(公告)号：US20090230481A1

公开(公告)日：2009-09-17

申请号：US12401693

申请日：2009-03-11

申请人： Jong-ho Park ,  Chang-ki Jeon ,  Kyijeong Park

发明人： Jong-ho Park ,  Chang-ki Jeon ,  Kyijeong Park

IPC分类号： H01L27/06 ,  H01L21/60 ,  H01L21/28 ,  H01L21/70

CPC分类号： H01L21/8249 ,  H01L21/2256 ,  H01L21/823814 ,  H01L27/0623

摘要： Provided are a semiconductor device including a source/drain and a gate formed using a doped polysilicon process, and a method of fabricating the semiconductor device. The method comprises: forming a gate insulating layer on a part of an active region on a first conductivity type epitaxial layer; forming a conductive layer on the epitaxial layer; implanting high concentration impurities of a second conductivity type a first portion of the conductive layer on the gate insulating layer and second portions of the conductive layer on both sides of the first insulating layer; patterning the conductive layer; forming a second insulating layer on the epitaxial layer and high concentration impurity regions of the second conductivity type below the second conductive pattern; and implanting low-concentration impurities of the second conductivity type into the epitaxial layer between a gate structure and the high concentration impurity regions.

摘要翻译： 提供了包括使用掺杂多晶硅工艺形成的源极/漏极和栅极的半导体器件，以及制造半导体器件的方法。 该方法包括：在第一导电型外延层的有源区的一部分上形成栅极绝缘层; 在外延层上形成导电层; 将第二导电类型的高浓度杂质注入到第一绝缘层的栅绝缘层上的导电层的第一部分和导电层的第二部分上; 图案化导电层; 在所述外延层上形成第二绝缘层，在所述第二导电图案之下形成所述第二导电类型的高浓度杂质区; 以及将第二导电类型的低浓度杂质注入到栅极结构和高浓度杂质区之间的外延层中。

公开(公告)号：US08399923B2

公开(公告)日：2013-03-19

申请号：US12495948

申请日：2009-07-01

申请人： Yong-cheol Choi ,  Chang-ki Jeon ,  Min-suk Kim

发明人： Yong-cheol Choi ,  Chang-ki Jeon ,  Min-suk Kim

IPC分类号： H01L29/66

CPC分类号： H01L29/66681 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/7816

摘要： Provided are a high voltage semiconductor device in which a field shaping layer is formed on the entire surface of a semiconductor substrate and a method of fabricating the same. Specifically, the high voltage semiconductor device includes a first conductivity-type semiconductor substrate. A second conductivity-type semiconductor layer is disposed on a surface of the semiconductor substrate, and a first conductivity-type body region is formed in semiconductor layer. A second conductivity-type source region is formed in the body region. A drain region is formed in the semiconductor layer and is separated from the body region. The field shaping layer is formed on the entire surface of the semiconductor layer facing the semiconductor layer.

摘要翻译： 提供一种在半导体衬底的整个表面上形成场成形层的高电压半导体器件及其制造方法。 具体地，高电压半导体器件包括第一导电型半导体衬底。 在半导体衬底的表面上设置第二导电型半导体层，在半导体层中形成第一导电型体区。 在体区域中形成第二导电型源极区域。 在半导体层中形成漏区，与体区分离。 在与半导体层相对的半导体层的整个表面上形成场成形层。

公开(公告)号：US07906828B2

公开(公告)日：2011-03-15

申请号：US12397426

申请日：2009-03-04

申请人： Sung-lyong Kim ,  Chang-ki Jeon

发明人： Sung-lyong Kim ,  Chang-ki Jeon

IPC分类号： H01L21/70

CPC分类号： H01L29/8611 ,  H01L27/0629 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/868 ,  H01L2924/0002 ,  H03K17/6877 ,  H03K2217/0036 ,  H01L2924/00

摘要： A high-voltage integrated circuit includes a low-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a ground voltage, a high-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a voltage that varies from the ground voltage to a high voltage, a junction termination and a first isolation region electrically isolating the low-voltage circuit region from the high-voltage circuit region, a high-voltage resistant diode formed between the low-voltage circuit region and the high-voltage circuit region, and a second isolation region surrounding the high-voltage resistant diode and electrically isolating the high-voltage resistant diode from the low-voltage circuit region and the high-voltage circuit region.

摘要翻译： 高压集成电路包括：具有多个相对于接地电压工作的半导体器件的低电压电路区域，具有多个半导体器件的高电压电路区域，其相对于 从接地电压到高压变化，接合端接和将低压电路区域与高压电路区域电隔离的第一隔离区域，形成在低压电路区域和低压电路区域之间的高耐压二极管 高压电路区域和围绕高耐压二极管的第二隔离区域，并且将高耐压二极管与低压电路区域和高压电路区域电隔离。

公开(公告)号：US20090243696A1

公开(公告)日：2009-10-01

申请号：US12402528

申请日：2009-03-12

申请人： Chang-ki Jeon ,  Min-suk Kim ,  Yong-cheol Choi

发明人： Chang-ki Jeon ,  Min-suk Kim ,  Yong-cheol Choi

IPC分类号： H03L5/00 ,  H01L21/76

CPC分类号： H01L27/088 ,  H01L21/823481

摘要： Provided are a high-voltage semiconductor device including a junction termination which electrically isolates a low voltage unit from a high voltage unit, and a method of fabricating the same. The high voltage semiconductor device includes a high voltage unit, a low voltage unit surrounding the high voltage unit, and a junction termination formed between the high voltage unit and the low voltage unit and surrounding the high voltage unit to electrically isolate the high voltage unit from the low voltage unit. The junction termination includes at least one level shifter which level shifts signals from the low voltage unit and supplies the same to the high voltage unit, a first device isolation region surrounding the high voltage unit to electrically isolate the high voltage unit from the level shifter, and a resistor layer electrically connecting neighboring level shifters.

摘要翻译： 提供一种包括将低电压单元与高电压单元电隔离的接合端子的高压半导体器件及其制造方法。 高电压半导体器件包括高电压单元，围绕高电压单元的低电压单元，以及形成在高电压单元和低电压单元之间并且围绕高电压单元的连接端子，以将高压单元与 低压单位。 所述连接终端包括至少一个电平移位器，其将来自所述低电压单元的信号电平移位并将其提供给所述高压单元;围绕所述高压单元的第一器件隔离区，以将所述高压单元与所述电平移位器电隔离; 以及电连接相邻电平移位器的电阻层。

公开(公告)号：US07518209B2

公开(公告)日：2009-04-14

申请号：US11378210

申请日：2006-03-16

申请人： Sung-lyong Kim ,  Chang-ki Jeon

发明人： Sung-lyong Kim ,  Chang-ki Jeon

IPC分类号： H01L29/93 ,  H01L23/58

CPC分类号： H01L29/8611 ,  H01L27/0629 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/868 ,  H01L2924/0002 ,  H03K17/6877 ,  H03K2217/0036 ,  H01L2924/00

摘要： Provided is a high-voltage integrated circuit device including a high-voltage resistant diode. The device includes a low-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a ground voltage, a high-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a voltage that varies from the ground voltage to a high voltage, a junction termination and a first isolation region electrically isolating the low-voltage circuit region from the high-voltage circuit region, a high-voltage resistant diode formed between the low-voltage circuit region and the high-voltage circuit region, and a second isolation region surrounding the high-voltage resistant diode and electrically isolating the high-voltage resistant diode from the low-voltage circuit region and the high-voltage circuit region. Therefore, a leakage current of the high-voltage resistant diode can be prevented.

摘要翻译： 提供一种包括耐高压二极管的高压集成电路装置。 该器件包括具有多个相对于接地电压工作的多个半导体器件的低电压电路区域，具有多个半导体器件的高电压电路区域，其相对于从地面变化的电压工作 电压到高电压，接合端接和将低压电路区域与高压电路区域电隔离的第一隔离区域，形成在低压电路区域和高压电路之间的高耐压二极管 以及围绕所述耐高压二极管的第二隔离区域，并且将所述耐高压二极管与所述低压电路区域和所述高压电路区域电隔离。 因此，可以防止高耐压二极管的漏电流。

公开(公告)号：US07309894B2

公开(公告)日：2007-12-18

申请号：US11114693

申请日：2005-04-26

申请人： Chang-ki Jeon ,  Sung-lyong Kim ,  Tae-hun Kwon

发明人： Chang-ki Jeon ,  Sung-lyong Kim ,  Tae-hun Kwon

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L29/7816 ,  H01L27/0629 ,  H01L29/0615 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/7823

摘要： There is provided a high voltage gate driver integrated circuit. The high voltage gate driver integrated circuit includes: a high voltage region; a junction termination region surrounding the high voltage region; a low voltage region surrounding the junction termination region; a level shift transistor disposed between the high voltage region and the low voltage region, at least some portions of the level shift transistor being overlapped with the junction termination region; and/or a high voltage junction capacitor disposed between the high voltage region and the low voltage region, at least some portions of the high voltage junction capacitor being overlapped with the junction termination region.

摘要翻译： 提供了高压栅极驱动器集成电路。 高压栅极驱动器集成电路包括：高电压区域; 围绕高电压区域的接合端接区域; 围绕所述连接端接区域的低电压区域; 设置在所述高电压区域和所述低电压区域之间的电平移位晶体管，所述电平移位晶体管的至少一些部分与所述连接终止区域重叠; 和/或设置在高电压区域和低电压区域之间的高压结电容器，高压结电容器的至少一些部分与接合端接区域重叠。

公开(公告)号：US06995453B2

公开(公告)日：2006-02-07

申请号：US10241818

申请日：2002-09-10

申请人： Jong-jib Kim ,  Chang-ki Jeon ,  Sung-lyong Kim ,  Young-suk Choi ,  Min-hwan Kim

发明人： Jong-jib Kim ,  Chang-ki Jeon ,  Sung-lyong Kim ,  Young-suk Choi ,  Min-hwan Kim

IPC分类号： H01L27/102 ,  H01L29/70

CPC分类号： H01L21/761 ,  H01L27/0623 ,  H01L29/7322

摘要： In a high voltage integrated circuit, a low voltage region is separated from a high voltage region by a junction termination. A bipolar transistor in the high voltage region is surrounded by an isolation region having a low doping concentration. The use of a low-doped isolation region increases the size of an active region without reduction of a breakdown voltage.

公开(公告)号：US20110014760A1

公开(公告)日：2011-01-20

申请号：US12890947

申请日：2010-09-27

申请人： Chang-ki Jeon ,  Gary Dolny

发明人： Chang-ki Jeon ,  Gary Dolny

IPC分类号： H01L21/336

CPC分类号： H01L29/7825 ,  H01L29/0634 ,  H01L29/0696

摘要： A method of forming a field effect transistor (FET) includes: forming a drift region comprising a stack of alternating conductivity type silicon layers; forming a drain region of a first conductivity type extending into the stack of alternating conductivity type silicon layers; forming a trench gate extending into the stack of alternating conductivity type silicon layers, the trench gate having a non-active sidewall and an active sidewall being perpendicular to one another; and forming a body region of a second conductivity type adjacent to the active sidewall of the trench gate, wherein the trench gate and the drain region are formed such that the non-active sidewall of the trench gate faces the drain region.

摘要翻译： 形成场效应晶体管（FET）的方法包括：形成包括交替导电型硅层叠层的漂移区; 形成延伸到交替导电型硅层堆叠中的第一导电类型的漏区; 形成延伸到交替导电型硅层的堆叠中的沟槽栅极，所述沟槽栅极具有非活性侧壁和主动侧壁彼此垂直; 以及形成与所述沟槽栅极的有源侧壁相邻的第二导电类型的主体区域，其中所述沟槽栅极和漏极区域形成为使得所述沟槽栅极的非有源侧壁面向所述漏极区域。