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    RESISTIVE RAM DEVICES AND METHODS
    1.
    发明申请
    RESISTIVE RAM DEVICES AND METHODS 有权
    电阻RAM设备和方法

    公开(公告)号：US20120267599A1

    公开(公告)日：2012-10-25

    申请号：US13517747

    申请日：2012-06-14

    申请人： Joseph N. Greeley ,  John A. Smythe, III

    发明人： Joseph N. Greeley ,  John A. Smythe, III

    IPC分类号： H01L47/00 ,  H01L21/02

    CPC分类号： H01L45/1683 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1633

    摘要： The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One method of forming an RRAM device includes forming a resistive element having a metal-metal oxide interface. Forming the resistive element includes forming an insulative material over the first electrode, and forming a via in the insulative material. The via is conformally filled with a metal material, and the metal material is planarized to within the via. A portion of the metal material within the via is selectively treated to create a metal-metal oxide interface within the via. A second electrode is formed over the resistive element.

    摘要翻译： 本公开包括高密度电阻随机存取存储器（RRAM）装置，以及制造高密度RRAM装置的方法。 形成RRAM器件的一种方法包括形成具有金属 - 金属氧化物界面的电阻元件。 形成电阻元件包括在第一电极上形成绝缘材料，以及在绝缘材料中形成通孔。 通孔由金属材料共形填充，并且金属材料被平坦化到通孔内。 通孔内的金属材料的一部分被选择性地处理以在通孔内产生金属 - 金属氧化物界面。 第二电极形成在电阻元件上。

    Method of fabricating a high quality thin oxide
    4.
    发明授权
    Method of fabricating a high quality thin oxide 有权
    制造高品质薄氧化物的方法

    公开(公告)号：US06190973B1

    公开(公告)日：2001-02-20

    申请号：US09215797

    申请日：1998-12-18

    申请人： John E. Berg ,  Bernice L. Kickel ,  John A. Smythe, III

    发明人： John E. Berg ,  Bernice L. Kickel ,  John A. Smythe, III

    IPC分类号： H01L218234

    CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L21/28273 ,  H01L29/42368 ,  H01L29/518

    摘要： The present invention provides a method of forming a high quality thin oxide on a semiconductor body. A sacrificial oxide is formed on the semiconductor and then etched to eliminate the surface contamination of the semiconductor body. Then, an EEPROM oxide is formed following by an arsenic implant. Next the EEPROM oxide on the semiconductor body is then prepared by thin oxide growth. The thin oxide is preferably formed in a steam ambient. Subsequently, the oxide is annealed under nitrous oxide ambient using a combination of in-situ and RTP annealing process.

    摘要翻译： 本发明提供了在半导体本体上形成高品质薄氧化物的方法。 在半导体上形成牺牲氧化物，然后蚀刻以消除半导体本体的表面污染。 然后，通过砷注入形成EEPROM氧化物。 接下来，通过薄氧化物生长制备半导体本体上的EEPROM氧化物。 薄氧化物优选在蒸汽环境中形成。 随后，使用原位和RTP退火工艺的组合，氧化物在一氧化二氮环境下进行退火。

    Trench isolation implantation
    5.
    发明授权
    Trench isolation implantation 有权
    沟槽隔离植入

    公开(公告)号：US08686535B2

    公开(公告)日：2014-04-01

    申请号：US12758488

    申请日：2010-04-12

    申请人： Gurtej S. Sandhu ,  John A. Smythe, III

    发明人： Gurtej S. Sandhu ,  John A. Smythe, III

    IPC分类号： H01L21/70

    CPC分类号： H01L21/76237 ,  G11C11/401 ,  H01L27/10844 ,  H01L27/11517

    摘要： Embodiments of the disclosure include a shallow trench isolation structure having a dielectric material with energetic species implanted to a predetermined depth of the dielectric material. Embodiments further include methods of fabricating the trench structures with the implant of energetic species to the predetermined depth. In various embodiments the implant of energetic species is used to densify the dielectric material to provide a uniform wet etch rate across the surface of the dielectric material. Embodiments also include memory devices, integrated circuits, and electronic systems that include shallow trench isolation structures having the dielectric material with the high flux of energetic species implanted to the predetermined depth of the dielectric material.

    摘要翻译： 本公开的实施例包括浅沟槽隔离结构，其具有将能量物质注入电介质材料的预定深度的电介质材料。 实施例还包括使能量物质的植入物到预定深度制造沟槽结构的方法。 在各种实施例中，能量物质的注入用于致密化电介质材料，以提供穿过电介质材料表面的均匀的湿蚀刻速率。 实施例还包括存储器件，集成电路和电子系统，其包括浅沟槽隔离结构，其具有植入到介电材料的预定深度的高能量物质的高通量的电介质材料。

    Isolation trench
    6.
    发明授权
    Isolation trench 有权
    隔离槽

    公开(公告)号：US07622769B2

    公开(公告)日：2009-11-24

    申请号：US11497665

    申请日：2006-08-01

    申请人： John A. Smythe, III ,  Jigish D. Trivedi

    发明人： John A. Smythe, III ,  Jigish D. Trivedi

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L21/76224

    摘要： A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an oxygen barrier is deposited into the trench. An expandable, oxidizable liner, preferably amorphous silicon, is then deposited. The trench is then filled with a spin-on dielectric (SOD) material. A densification process is then applied, whereby the SOD material contracts and the oxidizable liner expands. Preferably, the temperature is ramped up while oxidizing during at least part of the densification process. The resulting trench has a negligible vertical wet etch rate gradient and a negligible recess at the top of the trench.

    摘要翻译： 提供了将电介质材料沉积到亚微米空间和结构中的方法。 在晶片的表面中蚀刻沟槽之后，将氧势垒沉积到沟槽中。 然后沉积可膨胀的可氧化衬垫，优选非晶硅。 然后用旋涂电介质（SOD）材料填充沟槽。 然后施加致密化过程，由此SOD材料收缩并且可氧化衬里膨胀。 优选地，在致密化过程的至少部分期间，温度升高而氧化。 所形成的沟槽具有可忽略的垂直湿蚀刻速率梯度和在沟槽顶部的可忽略的凹陷。

    Trench insulation structures including an oxide liner that is thinner along the walls of the trench than along the base
    7.
    发明授权
    Trench insulation structures including an oxide liner that is thinner along the walls of the trench than along the base 有权
    沟槽绝缘结构包括沿着沟槽的壁比沿底部更薄的氧化物衬垫

    公开(公告)号：US07271463B2

    公开(公告)日：2007-09-18

    申请号：US11009665

    申请日：2004-12-10

    申请人： John A. Smythe, III ,  William Budge

    发明人： John A. Smythe, III ,  William Budge

    IPC分类号： H01L23/58

    CPC分类号： H01L21/76224

    摘要： A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited into the trench. An anisotropic plasma process is then performed on the trench. A silicon layer may be deposited on the base of the trench during the plasma process, or the plasma can treat the liner layer. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator, and oxidizing the silicon rich layer on the base of the trench. The resulting trench has a consistent etch rate from top to bottom of the trench.

    摘要翻译： 提供了将电介质材料沉积到亚微米空间和结构中的方法。 在晶片的表面中蚀刻沟槽之后，衬垫层优选沉积到沟槽中。 然后在沟槽上进行各向异性等离子体处理。 在等离子体工艺期间，硅层可以沉积在沟槽的基底上，或等离子体可以处理衬层。 然后用旋涂前体填充沟槽。 然后施加致密化或反应过程以将旋涂材料转化成绝缘体，并且氧化沟槽底部的富硅层。 所得到的沟槽具有从沟槽的顶部到底部的一致的蚀刻速率。

    Liner for shallow trench isolation
    10.
    发明授权
    Liner for shallow trench isolation 有权
    衬垫用于浅沟隔离

    公开(公告)号：US07271464B2

    公开(公告)日：2007-09-18

    申请号：US10925715

    申请日：2004-08-24

    申请人： Jigish D. Trivedi ,  Robert D. Patraw ,  Kevin L. Beaman ,  John A. Smythe, III

    发明人： Jigish D. Trivedi ,  Robert D. Patraw ,  Kevin L. Beaman ,  John A. Smythe, III

    IPC分类号： H01L29/00

    CPC分类号： H01L21/76224 ,  H01L21/76227

    摘要： A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content near the trench walls to protect the walls. The silicon nitride layer further from the trench walls has a low nitrogen content and a high silicon content, to allow improved adhesion. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator. The resulting trench has a well-adhered insulator which helps the insulating properties of the trench.

    摘要翻译： 提供了将电介质材料沉积到亚微米空间和结构中的方法。 在晶片的表面蚀刻沟槽之后，将氮化硅屏障沉积到沟槽中。 氮化硅层在沟壁附近具有高氮含量以保护壁。 进一步从沟槽壁的氮化硅层具有低的氮含量和高的硅含量，以提高粘附性。 然后用旋涂前体填充沟槽。 然后施加致密化或反应过程以将旋涂材料转化成绝缘体。 所得的沟槽具有良好粘附的绝缘体，其有助于沟槽的绝缘性能。