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23 条记录 (耗时 0.022 秒)

    Method of forming a spin-on-glass insulation layer
    2.
    发明授权
    Method of forming a spin-on-glass insulation layer 有权
    形成旋涂玻璃绝缘层的方法

    公开(公告)号：US06635586B2

    公开(公告)日：2003-10-21

    申请号：US09977673

    申请日：2001-10-15

    申请人： Ju-Seon Goo ,  Eun-Kee Hong ,  Hong-Gun Kim ,  Jin-Gi Hong

    发明人： Ju-Seon Goo ,  Eun-Kee Hong ,  Hong-Gun Kim ,  Jin-Gi Hong

    IPC分类号： H01L2469

    CPC分类号： H01L21/02282 ,  H01L21/02123 ,  H01L21/02222 ,  H01L21/02337 ,  H01L21/316 ,  H01L21/76819 ,  H01L21/76828 ,  H01L21/76837

    摘要： A method of forming a SOG insulation layer of a semiconductor device comprises forming the SOG insulation layer on a substrate having a stepped pattern by using a polysilazane in a solution state, performing a pre-bake process for removing solvent elements of the insulation layer at a temperature of 50 to 350° C., performing a hard bake process for restraining particles from forming at a temperature of 350 to 500° C., and annealing at a temperature of 600 to 1200° C. The method of the invention further includes planarizing the insulation layer between the hard bake process and the annealing step. Also, the hard bake process can be omitted.

    摘要翻译： 形成半导体器件的SOG绝缘层的方法包括：通过使用溶液状态的聚硅氮烷在具有阶梯状图案的基板上形成SOG绝缘层，进行用于除去绝缘层的溶剂元素的预烘烤工序 温度为50〜350℃，进行用于抑制微粒在350〜500℃的温度下形成的硬烘烤工艺，在600〜1200℃的温度下进行退火。本发明的方法还包括平面化 硬烘烤工艺与退火步骤之间的绝缘层。 此外，可以省略硬烘焙处理。

    Methods of filling gaps by deposition on materials having different deposition rates
    3.
    发明授权
    Methods of filling gaps by deposition on materials having different deposition rates 有权
    通过沉积在具有不同沉积速率的材料上填充间隙的方法

    公开(公告)号：US07358190B2

    公开(公告)日：2008-04-15

    申请号：US10732931

    申请日：2003-12-11

    申请人： Hong-gun Kim ,  Kyu-tae Na ,  Eun-Kee Hong ,  Ju-Seon Goo

    发明人： Hong-gun Kim ,  Kyu-tae Na ,  Eun-Kee Hong ,  Ju-Seon Goo

    IPC分类号： H01L21/311

    CPC分类号： H01L21/02164 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/31612 ,  H01L21/76224 ,  H01L21/76229

    摘要： Methods of forming material in a gap in a substrate include forming a pattern to define a gap on a substrate. A bottom oxide layer is formed on a surface of the substrate and substantially filling the gap. The bottom oxide layer is etched back inside an opening in the gap to expose side walls of the gap so that a residual bottom oxide layer remains at a bottom of the gap. A top oxide layer is selectively deposited on the residual bottom oxide layer, wherein the top oxide layer is deposited in a first direction toward the opening at a faster rate than in a second direction away from the side walls.

    摘要翻译： 在衬底中的间隙中形成材料的方法包括形成图案以在衬底上限定间隙。 底部氧化物层形成在衬底的表面上并且基本上填充间隙。 底部氧化物层在间隙中的开口内被回蚀，以暴露间隙的侧壁，使得剩余的底部氧化物层保留在间隙的底部。 顶部氧化物层被选择性地沉积在残余的底部氧化物层上，其中顶部氧化物层以比在远离侧壁的第二方向更快的速率沿第一方向朝向开口沉积。

    Method of forming a silicon oxide layer of a semiconductor device and method of forming a wiring having the same
    8.
    发明授权
    Method of forming a silicon oxide layer of a semiconductor device and method of forming a wiring having the same 有权
    形成半导体器件的氧化硅层的方法及其形成方法

    公开(公告)号：US06645879B2

    公开(公告)日：2003-11-11

    申请号：US10215309

    申请日：2002-08-08

    申请人： Eun-Kee Hong ,  Ju-Bum Lee ,  Ju-Seon Goo ,  Myeong-Cheol Kim ,  Hong-Gun Kim

    发明人： Eun-Kee Hong ,  Ju-Bum Lee ,  Ju-Seon Goo ,  Myeong-Cheol Kim ,  Hong-Gun Kim

    IPC分类号： H01L2131

    CPC分类号： H01L21/76897 ,  H01L21/31051 ,  H01L21/76819 ,  H01L21/76828 ,  H01L21/76834 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/0002 ,  Y10S438/935 ,  H01L2924/00

    摘要： Disclosed are methods for forming a silicon oxide layer of a semiconductor device capable of insulating between fine conductive patterns without causing a process failure, and for forming a wiring having the silicon oxide layer. After forming conductive patterns on a semiconductor substrate, an anti-oxidation layer is sequentially formed on the conductive patterns and on the semiconductor substrate. The anti-oxidation layer prevents an oxidant from penetrating into the conductive patterns and the semiconductor substrate. A reflowable oxide layer is formed by coating a reflowable oxidizing material on the anti-oxidation layer while burying the conductive patterns. The silicon oxide layer is formed by thermally treating the reflowable oxide layer. Then, the silicon oxide layer filled between conductive patterns and the anti-oxidation layer exposed to the semiconductor substrate are etched so as to form a contact hole, thereby forming the wiring of the semiconductor device. Thus, a planar silicon oxide layer is formed between conductive patterns having a fine interval therebetween without creating a void. In addition, a metal layer pattern, which acts as a conductor in the conductive patterns, can be prevented from being oxidized when the silicon oxide layer is formed.

    摘要翻译： 公开了用于形成能够在不导致工艺故障的细导电图案之间绝缘的半导体器件的氧化硅层的形成方法，以及用于形成具有氧化硅层的布线的方法。 在半导体衬底上形成导电图案之后，在导电图案和半导体衬底上依次形成抗氧化层。 抗氧化层防止氧化剂渗透到导电图案和半导体衬底中。 通过在抗氧化层上涂覆可回流氧化材料同时掩埋导电图案来形成可回流氧化物层。 通过热处理可回流氧化物层形成氧化硅层。 然后，在导电图案和暴露于半导体基板的抗氧化层之间填充的氧化硅层被蚀刻以形成接触孔，从而形成半导体器件的布线。 因此，在其间具有微细间隔的导电图案之间形成平面氧化硅层，而不产生空隙。 此外，当形成氧化硅层时，可以防止在导电图案中充当导体的金属层图案被氧化。

    Flash memory device and method of fabricating the same
    9.
    发明授权
    Flash memory device and method of fabricating the same 有权
    闪存装置及其制造方法

    公开(公告)号：US07842569B2

    公开(公告)日：2010-11-30

    申请号：US11618155

    申请日：2006-12-29

    申请人： Hong-Gun Kim ,  Ju-Seon Goo ,  Mun-Jun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

    发明人： Hong-Gun Kim ,  Ju-Seon Goo ,  Mun-Jun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

    IPC分类号： H01L21/00

    CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

    摘要： One embodiment of a method of fabricating a flash memory device includes forming a trench mask pattern, which includes a gate insulation pattern and a charge storage pattern stacked in sequence, on a semiconductor substrate; etching the semiconductor substrate using the trench mask pattern as an etch mask to form trenches defining active regions; and sequentially forming lower and upper device isolation patterns in the trench. After sequentially forming an intergate insulation film and a control gate film on the upper device isolation pattern, the control gate film, the intergate insulation pattern and the gloating gate pattern are formed, thereby providing gate lines crossing over the active regions.

    摘要翻译： 制造闪速存储器件的方法的一个实施例包括在半导体衬底上形成沟槽掩模图案，其包括依次层叠的栅极绝缘图案和电荷存储图案; 使用沟槽掩模图案作为蚀刻掩模蚀刻半导体衬底，以形成限定有源区的沟槽; 并且顺序地形成沟槽中的下部和上部器件隔离图案。 在上部器件隔离图案上顺序地形成栅极间绝缘膜和控制栅极膜之后，形成控制栅极膜，栅极间绝缘图案和阴极管栅极图案，从而提供跨越有源区域的栅极线。