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公开(公告)号：US08723260B1
公开(公告)日：2014-05-13
申请号：US12723257
申请日：2010-03-12
申请人： Michael Carroll , Daniel Charles Kerr , Christian Rye Iversen , Philip Mason , Julio Costa , Edward T. Spears
发明人： Michael Carroll , Daniel Charles Kerr , Christian Rye Iversen , Philip Mason , Julio Costa , Edward T. Spears
IPC分类号： H01L21/00
CPC分类号： H01L21/84 , H01L21/743 , H01L27/1203 , H01L29/4238 , H01L29/7833
摘要： The present disclosure relates to a radio frequency (RF) switch that includes multiple body-contacted field effect transistor (FET) elements coupled in series. The FET elements may be formed using a thin-film semiconductor device layer, which is part of a thin-film semiconductor die. Conduction paths between the FET elements through the thin-film semiconductor device layer and through a substrate of the thin-film semiconductor die may be substantially eliminated by using insulating materials. Elimination of the conduction paths allows an RF signal across the RF switch to be divided across the series coupled FET elements, such that each FET element is subjected to only a portion of the RF signal. Further, each FET element is body-contacted and may receive reverse body biasing when the RF switch is in an OFF state, thereby reducing an OFF state drain-to-source capacitance of each FET element.
摘要翻译： 本发明涉及射频（RF）开关，其包括串联耦合的多个体接触场效应晶体管（FET）元件。 可以使用作为薄膜半导体管芯的一部分的薄膜半导体器件层来形成FET元件。 通过薄膜半导体器件层和通过薄膜半导体晶片的衬底的FET元件之间的导通路径可以通过使用绝缘材料基本上消除。 消除导通路径允许跨越RF开关的RF信号在串联耦合的FET元件之间被分开，使得每个FET元件仅受到RF信号的一部分的影响。 此外，当RF开关处于OFF状态时，每个FET元件被体接触并且可以接收反向主体偏置，从而降低每个FET元件的截止状态漏极 - 源极电容。
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公开(公告)号：US07382030B1
公开(公告)日：2008-06-03
申请号：US11459829
申请日：2006-07-25
申请人： Tony Ivanov , Michael Carroll , Triet Dinh , Julio Costa
发明人： Tony Ivanov , Michael Carroll , Triet Dinh , Julio Costa
IPC分类号： H01L29/78
CPC分类号： H01L29/7835 , H01L29/1045 , H01L29/402 , H01L29/41775 , H01L29/66659
摘要： The present invention relates to a semiconductor device having an integrated metal shield. The shield, created as part of a MOSFET, is formed about a gate electrode of the MOSFET to effectively reduce drain-to-gate capacitance and increase breakdown voltage. The shield consists of a metallic shield contact via and a source contact extension. The metallic shield contact via, formed between the gate electrode and a drain region of the MOSFET, may be either a series of closely spaced vias or a wide continuous via. The metallic shield contact via is isolated from the surface of a semiconductor wafer by a shield isolation layer at one end. The metallic shield contact via is electrically coupled to the source contact extension at the other end. The source contact extension is metallic, and may be formed from the same metal used to create a source contact and a drain contact for the MOSFET.
摘要翻译： 本发明涉及具有集成金属屏蔽的半导体器件。 围绕MOSFET的栅极电极形成作为MOSFET的一部分而形成的屏蔽层，以有效地降低漏极 - 栅极电容并增加击穿电压。 屏蔽由金属屏蔽触点通孔和源触点延伸部组成。 形成在MOSFET的栅极电极和漏极区域之间的金属屏蔽接触通孔可以是一系列紧密间隔的通孔或宽的连续通孔。 金属屏蔽接触通孔通过一端的屏蔽隔离层与半导体晶片的表面隔离。 金属屏蔽接触通孔在另一端电耦合到源极接触延伸部。 源极接触延伸部是金属的，并且可以由用于产生MOSFET的源极接触和漏极接触的相同金属形成。
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公开(公告)号：US20120218047A1
公开(公告)日：2012-08-30
申请号：US13405481
申请日：2012-02-27
申请人： Julio Costa , Michael Carroll
发明人： Julio Costa , Michael Carroll
CPC分类号： H01L29/7325 , H01L23/66 , H01L29/0692 , H01L29/7371 , H01L2223/6644 , H01L2224/13022 , H01L2224/131 , H01L2224/13147 , H01L2224/16113 , H01L2224/16225 , H01L2224/16227 , H01L2924/01037 , H01L2924/1305 , H01L2924/014 , H01L2924/00
摘要： Power amplification devices are disclosed having a vertical ballast configuration to prevent thermal runaway in at least one stack of bipolar transistors formed on a semiconductor substrate. To provide a negative feedback to prevent thermal runaway in the bipolar transistors, a conductive layer is formed over and coupled to the stack. A resistivity of the conductive layer provides an effective resistance that prevents thermal runaway in the bipolar transistors. The vertical placement of the conductive layer allows for vertical heat dissipation and thus provides ballasting without concentrating heat.
摘要翻译： 公开了具有垂直镇流器配置的功率放大器件，以防止形成在半导体衬底上的至少一个双极晶体管堆叠中的热失控。 为了提供负反馈以防止双极晶体管中的热失控，导电层形成在堆叠上并耦合到堆叠。 导电层的电阻率提供了防止双极晶体管中的热失控的有效电阻。 导电层的垂直放置允许垂直散热，从而在不集中热的情况下提供压载。
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公开(公告)号：US09911836B2
公开(公告)日：2018-03-06
申请号：US13405481
申请日：2012-02-27
申请人： Julio Costa , Michael Carroll
发明人： Julio Costa , Michael Carroll
IPC分类号： H01L29/732 , H01L29/737 , H01L23/66 , H01L29/06
CPC分类号： H01L29/7325 , H01L23/66 , H01L29/0692 , H01L29/7371 , H01L2223/6644 , H01L2224/13022 , H01L2224/131 , H01L2224/13147 , H01L2224/16113 , H01L2224/16225 , H01L2224/16227 , H01L2924/01037 , H01L2924/1305 , H01L2924/014 , H01L2924/00
摘要： Power amplification devices are disclosed having a vertical ballast configuration to prevent thermal runaway in at least one stack of bipolar transistors formed on a semiconductor substrate. To provide a negative feedback to prevent thermal runaway in the bipolar transistors, a conductive layer is formed over and coupled to the stack. A resistivity of the conductive layer provides an effective resistance that prevents thermal runaway in the bipolar transistors. The vertical placement of the conductive layer allows for vertical heat dissipation and thus provides ballasting without concentrating heat.
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公开(公告)号：US07772648B1
公开(公告)日：2010-08-10
申请号：US11854068
申请日：2007-09-12
IPC分类号： H01L29/72
CPC分类号： H01L29/7317 , H01L27/1203 , H01L29/66265
摘要： The present invention includes a silicon-on-insulator (SOI) wafer that enhances certain performance parameters by increasing silicon device layer and insulator layer thicknesses and increasing silicon handle wafer resistivity. By increasing the silicon device layer thickness, effects of the floating body problem may be significantly reduced. By increasing the insulator layer thickness and the silicon handle wafer resistivity, influences from the silicon handle wafer on devices formed using the silicon device layer may be significantly reduced. As a result, standard tools, methods, and processes may be used.
摘要翻译： 本发明包括通过增加硅器件层和绝缘体层厚度并增加硅处理晶片电阻率来增强某些性能参数的绝缘体上硅（SOI）晶片。 通过增加硅器件层厚度，浮体问题的影响可能会大大降低。 通过增加绝缘体层厚度和硅处理晶片电阻率，可以显着地减少硅处理晶片对使用硅器件层形成的器件的影响。 因此，可以使用标准工具，方法和过程。
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公开(公告)号：US07135766B1
公开(公告)日：2006-11-14
申请号：US10999314
申请日：2004-11-30
申请人： Julio Costa , Tony Ivanov , Michael Carroll
发明人： Julio Costa , Tony Ivanov , Michael Carroll
IPC分类号： H01L23/12 , H01L23/053
CPC分类号： H01L24/10 , H01L23/3677 , H01L23/50 , H01L23/5286 , H01L23/66 , H01L24/13 , H01L2223/6622 , H01L2224/05001 , H01L2224/05022 , H01L2224/05572 , H01L2224/056 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2224/16235 , H01L2924/00014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/014 , H01L2924/1305 , H01L2924/1306 , H01L2924/30107 , H01L2924/3025 , H01L2924/00 , H01L2224/05099
摘要： A flip chip power device having an integrated low inductance ground and heat sink path and an isolation structure is provided. A substrate is formed having transistors and an ohmic contact region circumscribing the transistors. Dielectric layers are formed on the substrate, and a common metal layer is formed on the dielectric layers. An isolation metal layer is formed on the dielectric layers above the ohmic contact region. The common metal layer is coupled to a first region of each of the transistors, and the isolation metal layer is coupled to the ohmic contact region. A first bump is formed on the common metal layer, and a second bump is formed on the isolation metal layer. When the power device is attached to a second substrate, the first bump forms a low inductance ground and heat sink path to the second substrate, and an isolation structure is formed.
摘要翻译： 提供具有集成的低电感接地和散热路径以及隔离结构的倒装芯片功率器件。 形成具有晶体管和限制晶体管的欧姆接触区域的衬底。 在基板上形成介电层，在电介质层上形成共同的金属层。 在欧姆接触区上方的电介质层上形成隔离金属层。 公共金属层耦合到每个晶体管的第一区域，并且隔离金属层耦合到欧姆接触区域。 在公共金属层上形成第一凸块，在隔离金属层上形成第二凸块。 当功率器件附接到第二衬底时，第一凸块形成到第二衬底的低电感接地和散热通路，并且形成隔离结构。
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公开(公告)号：US11173943B2
公开(公告)日：2021-11-16
申请号：US16622874
申请日：2018-06-18
摘要： A portable storage sled for transporting equipment includes a first elongated member and a second elongated member. At least one connecting member joins the first elongated member to the second elongated member. Each of the first elongated member and the second elongated member includes an extension member that is selectively retractable and extendable therefrom. The first elongated member, the second elongated member, the first extension member and the second extension member include a plurality of ridges extending upwardly therefrom that form an equipment mount between which the equipment is situated. The portable storage sled is selectively adjustable in length and width so that equipment of various sizes can be situated thereon.
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公开(公告)号：US09356144B1
公开(公告)日：2016-05-31
申请号：US12854563
申请日：2010-08-11
CPC分类号： H01L29/7841 , H01L27/0255
摘要： The present disclosure relates to gate oxide protection circuits, which are used to protect the gate oxides of field effect transistor (FET) elements from over voltage conditions, particularly during situations in which the gate oxides are particularly vulnerable, such as during certain manufacturing stages. Each gate oxide protection circuit may be coupled to a corresponding FET element through corresponding first and second resistive elements, which are coupled to a corresponding gate connection node and a corresponding first connection node, respectively, of the FET element. The gate connection node and the first connection node are electrically adjacent to opposite sides of the gate oxide of the FET element. Each gate oxide protection circuit may protect its corresponding FET element by limiting a voltage between the gate connection node and the first connection node.
摘要翻译： 本公开涉及栅极氧化物保护电路，其用于保护场效应晶体管（FET）元件的栅极氧化物免受过电压条件，特别是在栅极氧化物特别容易受到影响的情况下，例如在某些制造阶段。 每个栅极氧化物保护电路可以通过对应的第一和第二电阻元件耦合到对应的FET元件，该第一和第二电阻元件分别耦合到FET元件的对应的栅极连接节点和相应的第一连接节点。 栅极连接节点和第一连接节点与FET元件的栅极氧化物的相对侧电气相邻。 每个栅极氧化物保护电路可以通过限制栅极连接节点和第一连接节点之间的电压来保护其对应的FET元件。
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公开(公告)号：US08076750B1
公开(公告)日：2011-12-13
申请号：US12958494
申请日：2010-12-02
IPC分类号： H01L29/00
CPC分类号： H01L23/645 , H01L23/5227 , H01L23/552 , H01L23/66 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to using a trap-rich layer, such as a polycrystalline Silicon layer, over a semiconductor substrate to substantially immobilize a surface conduction layer at the surface of the semiconductor substrate at radio frequency (RF) frequencies. The trap-rich layer may have a high density of traps that trap carriers from the surface conduction layer. The average release time from the traps may be longer than the period of any present RF signals, thereby effectively immobilizing the surface conduction layer, which may substantially prevent capacitance and inductance changes due to the RF signals. Therefore, harmonic distortion of the RF signals may be significantly reduced or eliminated. The semiconductor substrate may be a Silicon substrate, a Gallium Arsenide substrate, or another substrate.
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10.发明授权Linearity improvements of semiconductor substrate based radio frequency devices 有权基于半导体衬底的射频器件的线性改善公开(公告)号：US07868419B1
公开(公告)日：2011-01-11
申请号：US12254499
申请日：2008-10-20
IPC分类号： H01L27/08
CPC分类号： H01L23/645 , H01L23/5227 , H01L23/552 , H01L23/66 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to using a trap-rich layer, such as a polycrystalline Silicon layer, over a semiconductor substrate to substantially immobilize a surface conduction layer at the surface of the semiconductor substrate at radio frequency (RF) frequencies. The trap-rich layer may have a high density of traps that trap carriers from the surface conduction layer. The average release time from the traps may be longer than the period of any present RF signals, thereby effectively immobilizing the surface conduction layer, which may substantially prevent capacitance and inductance changes due to the RF signals. Therefore, harmonic distortion of the RF signals may be significantly reduced or eliminated. The semiconductor substrate may be a Silicon substrate, a Gallium Arsenide substrate, or another substrate.
摘要翻译： 本发明涉及在半导体衬底上使用诸如多晶硅层的富集层，以基本上以射频（RF）频率固定在半导体衬底的表面处的表面传导层。 富集阱层可具有高密度的陷阱，其将载流子从表面传导层捕获。 来自陷阱的平均释放时间可以比任何现有RF信号的周期长，从而有效地固定表面传导层，这可以基本上防止由于RF信号引起的电容和电感变化。 因此，可以显着地减少或消除RF信号的谐波失真。 半导体衬底可以是硅衬底，砷化镓衬底或另一衬底。
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