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    Nonlinear stepped programming voltage
    2.
    发明授权
    Nonlinear stepped programming voltage 有权
    非线性步进编程电压

    公开(公告)号：US06327183B1

    公开(公告)日：2001-12-04

    申请号：US09480868

    申请日：2000-01-10

    申请人： Joseph G. Pawletko ,  K. Michael Han ,  Narbeh Derhacobian

    发明人： Joseph G. Pawletko ,  K. Michael Han ,  Narbeh Derhacobian

    IPC分类号： G11C700

    CPC分类号： G11C5/147 ,  G11C16/12 ,  G11C16/3468

    摘要： A voltage control circuit that narrows the distribution of threshold voltages of memory cells by using nonlinearly incremented programming voltages. To do so, the voltage control circuit applies to the memory cells a first program pulse of a first voltage, a second program pulse of a second voltage to the memory cell, and a third program pulse of a third voltage, where the difference between the third voltage and the second voltage is less than the difference between the second voltage and the first voltage.

    摘要翻译： 一种电压控制电路，其通过使用非线性递增的编程电压来缩小存储器单元的阈值电压的分布。 为此，电压控制电路向存储器单元施加第一电压的第一编程脉冲，到存储单元的第二电压的第二编程脉冲和第三电压的第三编程脉冲， 第三电压，第二电压小于第二电压和第一电压之间的差。

    Using a negative gate erase voltage applied in steps of decreasing amounts to reduce erase time for a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure
    3.
    发明授权
    Using a negative gate erase voltage applied in steps of decreasing amounts to reduce erase time for a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure 失效
    使用以减少量的步骤施加的负栅极擦除电压以减少具有氧化物 - 氧化物 - 氧化物（ONO）结构的非易失性存储单元的擦除时间

    公开(公告)号：US06549466B1

    公开(公告)日：2003-04-15

    申请号：US09657143

    申请日：2000-09-07

    申请人： Narbeh Derhacobian ,  Michael Van Buskirk ,  Chi Chang ,  Daniel Sobek

    发明人： Narbeh Derhacobian ,  Michael Van Buskirk ,  Chi Chang ,  Daniel Sobek

    IPC分类号： G11C1604

    CPC分类号： G11C16/14

    摘要： An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure by using a negative gate erase voltage during an erase procedure to improve the speed and performance of the non-volatile memory cell after many program-erase cycles. During the erase procedure, an erase cycle is applied followed by a read cycle until the cell has a threshold erased below a desired value. For the initial erase cycle in the procedure, an initial negative gate voltage is applied. In subsequent erase cycles, a sequentially decreasing negative gate voltage is applied until the threshold is reduced below the desired value. In one embodiment, after erase is complete, the last negative gate voltage value applied is stored in a separate memory. After a subsequent programming when the erase procedure is again applied, the initial negative gate voltage applied is the negative gate voltage value for the cell stored in memory.

    摘要翻译： 在擦除过程中通过使用负栅极擦除电压在具有氧化物 - 氮化物 - 氧化物结构的非易失性存储单元上执行擦除操作，以在许多编程擦除周期之后提高非易失性存储单元的速度和性能 。 在擦除过程期间，应用擦除周期，随后读取周期，直到单元具有低于期望值的阈值。 对于程序中的初始擦除周期，施加初始负栅极电压。 在随后的擦除周期中，施加顺序减小的负栅极电压，直到阈值降低到期望值以下。 在一个实施例中，在擦除完成之后，施加的最后一个负栅极电压值被存储在单独的存储器中。 在再次施加擦除过程之后的后续编程之后，施加的初始负栅极电压是存储在存储器中的单元的负栅极电压值。

    Nonvolatile memory cell with a nitridated oxide layer
    5.
    发明授权
    Nonvolatile memory cell with a nitridated oxide layer 有权
    具有氮化氧化物层的非挥发性存储单元

    公开(公告)号：US06750157B1

    公开(公告)日：2004-06-15

    申请号：US10199793

    申请日：2002-07-19

    申请人： Richard M. Fastow ,  Chi Chang ,  Narbeh Derhacobian

    发明人： Richard M. Fastow ,  Chi Chang ,  Narbeh Derhacobian

    IPC分类号： H01L2131

    CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L21/28282 ,  H01L21/3144 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/518

    摘要： One aspect of the present invention relates to a system and method for improving memory retention in flash memory devices. Retention characteristics may be enhanced by nitridating the bottom silicon dioxide layer of the ONO dielectric. To further mitigate charge leakage within the memory cell, the charge retention layer, or silicon nitride layer of the ONO dielectric, may be passivated via a hydrogen anneal process in order to reduce the number of charge traps, and thus, the amount of charge loss. The present invention also provides a monitoring and feedback-relay system to automatically control ONO formation such that a desired ONO dielectric stack is obtained. The present invention may be accomplished in part by employing a measurement system to measure properties and characteristics of the ONO stack during the critical formation steps of the bottom silicon dioxide layer and a silicon nitride layer.

    摘要翻译： 本发明的一个方面涉及用于改善闪存设备中的存储器保持的系统和方法。 可以通过对ONO电介质的底部二氧化硅层进行氮化来增强保留特性。 为了进一步减轻存储单元内的电荷泄漏，ONO电介质的电荷保持层或氮化硅层可以通过氢退火工艺被钝化，以减少电荷陷阱的数量，从而减少电荷损失量 。 本发明还提供了一种监测和反馈中继系统，用于自动控制ONO形成，从而获得所需的ONO电介质叠层。 本发明可以部分地通过使用测量系统在底部二氧化硅层和氮化硅层的临界形成步骤期间测量ONO堆叠的性质和特性来实现。

    Using a negative gate erase to increase the cycling endurance of a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure
    6.
    发明授权
    Using a negative gate erase to increase the cycling endurance of a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure 有权
    使用负栅极擦除来增加具有氧化物 - 氧化物 - 氧化物（ONO）结构的非易失性存储单元的循环耐久性

    公开(公告)号：US06381179B1

    公开(公告)日：2002-04-30

    申请号：US09656675

    申请日：2000-09-07

    申请人： Narbeh Derhacobian ,  Michael Van Buskirk ,  Chi Chang ,  Daniel Sobek

    发明人： Narbeh Derhacobian ,  Michael Van Buskirk ,  Chi Chang ,  Daniel Sobek

    IPC分类号： G11C1604

    CPC分类号： G11C16/14 ,  G11C16/0416

    摘要： An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure by using an initial negative gate erase voltage to improve the speed and performance of the non-volatile memory cell after many program-erase cycles. By utilizing a negative gate erase voltage, the cell does not require increased erase time to reduce the cell threshold and avoid incomplete erase conditions as the number of program-erase cycles increases.

    摘要翻译： 通过使用初始负栅极擦除电压对具有氧化物 - 氮化物 - 氧化物结构的非易失性存储单元进行擦除操作，以在许多编程擦除周期之后提高非易失性存储单元的速度和性能。 通过利用负栅极擦除电压，随着编程擦除周期数的增加，单元不需要增加的擦除时间来减小单元阈值并避免不完全的擦除条件。

    Circuits having programmable impedance elements
    7.
    发明授权
    Circuits having programmable impedance elements 有权
    具有可编程阻抗元件的电路

    公开(公告)号：US08687403B1

    公开(公告)日：2014-04-01

    申请号：US13157713

    申请日：2011-06-10

    申请人： Narbeh Derhacobian ,  Shane Charles Hollmer ,  Ishai Naveh

    发明人： Narbeh Derhacobian ,  Shane Charles Hollmer ,  Ishai Naveh

    IPC分类号： G11C11/00

    CPC分类号： H01L45/085 ,  G11C11/005 ,  G11C13/0007 ,  G11C13/0011 ,  G11C14/0045 ,  G11C14/009

    摘要： An integrated circuit (IC) device may include a first portion having a plurality of volatile memory cells; and a second portion coupled by a data transfer path to the first portion, the second portion including a plurality of nonvolatile memory cells, each nonvolatile memory cell including at least one resistive element programmable more than once between different resistance values. A memory device may also include variable impedance elements accessible by access bipolar junction transistors (BJTs) having at least a portion formed by a semiconductor layer formed over a substrate. A memory device may also include a plurality of memory elements that each includes a dielectric layer formed between a first and second electrode, the dielectric layer including a solid electrolyte with a soluble metal having a mobility less than that of silver in a germanium disulfide.

    摘要翻译： 集成电路（IC）装置可以包括具有多个易失性存储器单元的第一部分; 以及第二部分，其通过数据传输路径耦合到所述第一部分，所述第二部分包括多个非易失性存储器单元，每个非易失性存储单元包括在不同电阻值之间不止一次可编程的至少一个电阻元件。 存储器件还可以包括可由存取双极结型晶体管（BJT）访问的可变阻抗元件，其中至少一部分由形成在衬底上的半导体层形成。 存储器件还可以包括多个存储器元件，每个存储器元件包括形成在第一和第二电极之间的电介质层，该电介质层包括具有小于二硫化锗中银的迁移率的可溶性金属的固体电解质。

    Charge injection
    8.
    发明授权
    Charge injection 有权
    电荷注入

    公开(公告)号：US06567303B1

    公开(公告)日：2003-05-20

    申请号：US10050483

    申请日：2002-01-16

    申请人： Darlene G. Hamilton ,  Janet S. Y. Wang ,  Narbeh Derhacobian ,  Tim Thurgate ,  Michael K. Han

    发明人： Darlene G. Hamilton ,  Janet S. Y. Wang ,  Narbeh Derhacobian ,  Tim Thurgate ,  Michael K. Han

    IPC分类号： G11C1604

    CPC分类号： G11C16/3409 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/3404 ,  G11C16/3436 ,  G11C16/3445

    摘要： A system and methodology is provided for programming first and second bits of a memory array of dual bit memory cells at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. At a substantially higher delta VT, programming of the first bit of the memory cell causes the second bit to program harder and faster due to the shorter channel length. Therefore, the present invention employs selected gate and drain voltages and programming pulse widths during programming of the first and second bit that assures a controlled first bit VT and slows down programming of the second bit. Furthermore, the selected programming parameters keep the programming times short without degrading charge loss.

    摘要翻译： 提供了一种用于以基本上高的delta VT对双位存储器单元的存储器阵列的第一和第二位进行编程的系统和方法。 基本上更高的VT确保存储器阵列将维持编程数据并且在相当长的一段时间内在较高的温度应力和/或客户操作之后一致地擦除数据。 在基本上较高的增量VT下，存储器单元的第一位的编程使得第二位由于较短的通道长度而更硬更快地编程。 因此，本发明在第一和第二位的编程期间采用选择的栅极和漏极电压以及编程脉冲宽度，以确保受控的第一位VT并减慢第二位的编程。 此外，所选择的编程参数保持编程时间短而不降低电荷损耗。

    Single bit array edges
    9.
    发明授权
    Single bit array edges 有权
    单位阵列边缘

    公开(公告)号：US06493261B1

    公开(公告)日：2002-12-10

    申请号：US09795865

    申请日：2001-02-28

    申请人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Ravi Sunkavalli ,  Narbeh Derhacobian ,  Michael A. Van Buskirk

    发明人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Ravi Sunkavalli ,  Narbeh Derhacobian ,  Michael A. Van Buskirk

    IPC分类号： G11C1604

    CPC分类号： G11C16/3409 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/344 ,  G11C16/3445 ,  H01L27/115

    摘要： Dummy columns of memory cells formed during fabrication outside edge columns are connected to the actual used memory cells of sectors or the like. The columns of dummy memory cells are compensated by floating the dummy memory cells during normal programming and erase cycles, or alternatively, by programming and erasing the dummy memory cells along with the actual used memory cells in the sector. By treating the dummy memory cells similar to the actual used cells, charge that leaks into the dummy cells during fabrication and normal operation that has deleterious effects at higher stress temperatures and/or due to the longevity of customer operation is substantially eliminated.

    摘要翻译： 在制造外边缘列时形成的存储单元的虚拟柱被连接到扇区等的实际使用的存储单元。 虚拟存储单元的列通过在正常编程和擦除周期期间浮置伪存储单元来补偿，或者通过编程和擦除虚存储单元以及扇区中的实际使用的存储单元来补偿。 通过处理类似于实际使用的电池的虚拟存储器单元，在制造和正常操作期间泄漏到虚拟电池中的电荷在较高应力温度和/或由于客户操作的寿命而具有有害影响的基本上被消除。