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    Using a negative gate erase voltage applied in steps of decreasing amounts to reduce erase time for a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure
    2.
    发明授权
    Using a negative gate erase voltage applied in steps of decreasing amounts to reduce erase time for a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure 失效
    使用以减少量的步骤施加的负栅极擦除电压以减少具有氧化物 - 氧化物 - 氧化物（ONO）结构的非易失性存储单元的擦除时间

    公开(公告)号：US06549466B1

    公开(公告)日：2003-04-15

    申请号：US09657143

    申请日：2000-09-07

    申请人： Narbeh Derhacobian ,  Michael Van Buskirk ,  Chi Chang ,  Daniel Sobek

    发明人： Narbeh Derhacobian ,  Michael Van Buskirk ,  Chi Chang ,  Daniel Sobek

    IPC分类号： G11C1604

    CPC分类号： G11C16/14

    摘要： An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure by using a negative gate erase voltage during an erase procedure to improve the speed and performance of the non-volatile memory cell after many program-erase cycles. During the erase procedure, an erase cycle is applied followed by a read cycle until the cell has a threshold erased below a desired value. For the initial erase cycle in the procedure, an initial negative gate voltage is applied. In subsequent erase cycles, a sequentially decreasing negative gate voltage is applied until the threshold is reduced below the desired value. In one embodiment, after erase is complete, the last negative gate voltage value applied is stored in a separate memory. After a subsequent programming when the erase procedure is again applied, the initial negative gate voltage applied is the negative gate voltage value for the cell stored in memory.

    摘要翻译： 在擦除过程中通过使用负栅极擦除电压在具有氧化物 - 氮化物 - 氧化物结构的非易失性存储单元上执行擦除操作，以在许多编程擦除周期之后提高非易失性存储单元的速度和性能 。 在擦除过程期间，应用擦除周期，随后读取周期，直到单元具有低于期望值的阈值。 对于程序中的初始擦除周期，施加初始负栅极电压。 在随后的擦除周期中，施加顺序减小的负栅极电压，直到阈值降低到期望值以下。 在一个实施例中，在擦除完成之后，施加的最后一个负栅极电压值被存储在单独的存储器中。 在再次施加擦除过程之后的后续编程之后，施加的初始负栅极电压是存储在存储器中的单元的负栅极电压值。

    Nonvolatile memory cell with a nitridated oxide layer
    4.
    发明授权
    Nonvolatile memory cell with a nitridated oxide layer 有权
    具有氮化氧化物层的非挥发性存储单元

    公开(公告)号：US06750157B1

    公开(公告)日：2004-06-15

    申请号：US10199793

    申请日：2002-07-19

    申请人： Richard M. Fastow ,  Chi Chang ,  Narbeh Derhacobian

    发明人： Richard M. Fastow ,  Chi Chang ,  Narbeh Derhacobian

    IPC分类号： H01L2131

    CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L21/28282 ,  H01L21/3144 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/518

    摘要： One aspect of the present invention relates to a system and method for improving memory retention in flash memory devices. Retention characteristics may be enhanced by nitridating the bottom silicon dioxide layer of the ONO dielectric. To further mitigate charge leakage within the memory cell, the charge retention layer, or silicon nitride layer of the ONO dielectric, may be passivated via a hydrogen anneal process in order to reduce the number of charge traps, and thus, the amount of charge loss. The present invention also provides a monitoring and feedback-relay system to automatically control ONO formation such that a desired ONO dielectric stack is obtained. The present invention may be accomplished in part by employing a measurement system to measure properties and characteristics of the ONO stack during the critical formation steps of the bottom silicon dioxide layer and a silicon nitride layer.

    摘要翻译： 本发明的一个方面涉及用于改善闪存设备中的存储器保持的系统和方法。 可以通过对ONO电介质的底部二氧化硅层进行氮化来增强保留特性。 为了进一步减轻存储单元内的电荷泄漏，ONO电介质的电荷保持层或氮化硅层可以通过氢退火工艺被钝化，以减少电荷陷阱的数量，从而减少电荷损失量 。 本发明还提供了一种监测和反馈中继系统，用于自动控制ONO形成，从而获得所需的ONO电介质叠层。 本发明可以部分地通过使用测量系统在底部二氧化硅层和氮化硅层的临界形成步骤期间测量ONO堆叠的性质和特性来实现。

    Using a negative gate erase to increase the cycling endurance of a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure
    5.
    发明授权
    Using a negative gate erase to increase the cycling endurance of a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure 有权
    使用负栅极擦除来增加具有氧化物 - 氧化物 - 氧化物（ONO）结构的非易失性存储单元的循环耐久性

    公开(公告)号：US06381179B1

    公开(公告)日：2002-04-30

    申请号：US09656675

    申请日：2000-09-07

    申请人： Narbeh Derhacobian ,  Michael Van Buskirk ,  Chi Chang ,  Daniel Sobek

    发明人： Narbeh Derhacobian ,  Michael Van Buskirk ,  Chi Chang ,  Daniel Sobek

    IPC分类号： G11C1604

    CPC分类号： G11C16/14 ,  G11C16/0416

    摘要： An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure by using an initial negative gate erase voltage to improve the speed and performance of the non-volatile memory cell after many program-erase cycles. By utilizing a negative gate erase voltage, the cell does not require increased erase time to reduce the cell threshold and avoid incomplete erase conditions as the number of program-erase cycles increases.

    摘要翻译： 通过使用初始负栅极擦除电压对具有氧化物 - 氮化物 - 氧化物结构的非易失性存储单元进行擦除操作，以在许多编程擦除周期之后提高非易失性存储单元的速度和性能。 通过利用负栅极擦除电压，随着编程擦除周期数的增加，单元不需要增加的擦除时间来减小单元阈值并避免不完全的擦除条件。

    Computer system and processor having integrated phone functionality
    7.
    发明授权
    Computer system and processor having integrated phone functionality 有权
    具有集成手机功能的计算机系统和处理器

    公开(公告)号：US09106734B2

    公开(公告)日：2015-08-11

    申请号：US13584527

    申请日：2012-08-13

    申请人： Chi Chang

    发明人： Chi Chang

    IPC分类号： H04M11/00 ,  H04M1/247 ,  G06F3/02 ,  G06F3/023 ,  G06F3/0489

    CPC分类号： H04M1/2473 ,  G06F3/021 ,  G06F3/023 ,  G06F3/0489

    摘要： A computer system including telephone functionality. The computer system includes a first keyboard and a first display. The computer system also includes a processor having at least a first functional unit and a second functional unit, and further includes a phone portion. The computer system may operate in a first mode, a second mode, or a third mode. In the first mode, only the phone portion is activated, and the phone portion provides a functionality of placing and receiving phone calls without being removed from the computer system. In the second mode, the phone portion and first functional unit of the processor are activated. In the third mode, each of the phone portion, the first functional unit, and the second functional unit are activated.

    摘要翻译： 包括电话功能的计算机系统。 计算机系统包括第一键盘和第一显示器。 计算机系统还包括具有至少第一功能单元和第二功能单元的处理器，并且还包括电话部分。 计算机系统可以在第一模式，第二模式或第三模式中操作。 在第一模式中，只有电话部分被激活，并且电话部分提供放置和接收电话呼叫的功能，而不从计算机系统移除。 在第二模式中，处理器的电话部分和第一功能单元被激活。 在第三模式中，电话部分，第一功能单元和第二功能单元中的每一个被激活。

    Dual charge storage node memory device and methods for fabricating such device
    9.
    发明授权
    Dual charge storage node memory device and methods for fabricating such device 有权
    双电荷存储节点存储器件及其制造方法

    公开(公告)号：US07915123B1

    公开(公告)日：2011-03-29

    申请号：US11408866

    申请日：2006-04-20

    申请人： Chungho Lee ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Kyunghoon Min ,  Chi Chang

    发明人： Chungho Lee ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Kyunghoon Min ,  Chi Chang

    IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7883 ,  H01L29/792 ,  Y10S438/954

    摘要： A dual node memory device and methods for fabricating the device are provided. In one embodiment the method comprises forming a layered structure with an insulator layer, a charge storage layer, a buffer layer, and a sacrificial layer on a semiconductor substrate. The layers are patterned to form two spaced apart stacks and an exposed substrate portion between the stacks. A gate insulator and a gate electrode are formed on the exposed substrate, and the sacrificial layer and buffer layer are removed. An additional insulator layer is deposited overlying the charge storage layer to form insulator-storage layer-insulator memory storage areas on each side of the gate electrode. Sidewall spacers are formed at the sidewalls of the gate electrode overlying the storage areas. Bit lines are formed in the substrate spaced apart from the gate electrode, and a word line is formed that contacts the gate electrode and the sidewall spacers.

    摘要翻译： 提供了一种双节点存储器件及其制造方法。 在一个实施例中，该方法包括在半导体衬底上形成具有绝缘体层，电荷存储层，缓冲层和牺牲层的分层结构。 这些层被图案化以形成两个间隔开的堆叠和在堆叠之间的暴露的衬底部分。 在暴露的基板上形成栅极绝缘体和栅电极，去除牺牲层和缓冲层。 沉积覆盖电荷存储层的另外的绝缘体层，以在栅电极的每一侧上形成绝缘体存储层 - 绝缘体存储器存储区域。 侧壁间隔件形成在覆盖存储区域的栅电极的侧壁上。 在与栅极间隔开的衬底中形成位线，并且形成与栅电极和侧壁间隔物接触的字线。

    P-channel NAND in isolated N-well
    10.
    发明授权
    P-channel NAND in isolated N-well 有权
    隔离N阱中的P沟道NAND

    公开(公告)号：US07671403B2

    公开(公告)日：2010-03-02

    申请号：US11567257

    申请日：2006-12-06

    申请人： Wei Zheng ,  Chi Chang ,  Mark Randolph ,  Satoshi Torii

    发明人： Wei Zheng ,  Chi Chang ,  Mark Randolph ,  Satoshi Torii

    IPC分类号： H01L29/792

    CPC分类号： H01L27/115 ,  H01L27/11568

    摘要： A device includes a substrate and multiple wells formed over the substrate and isolated from one another by dielectric trenches. The device further includes multiple memory elements formed over the wells, each of the memory elements extending approximately perpendicular to the wells and including a material doped with n-type impurities. The device also includes multiple source/drain regions, each source/drain region formed within one of multiple trenches and inside one of the plurality of wells between a pair of the memory elements, each of the source/drain regions implanted with p-type impurities. The device further includes a first substrate contact formed in a first one of the multiple trenches through a first one of the wells into the substrate and a second substrate contact formed in a second one of the multiple trenches through a second one of the wells into the substrate.

    摘要翻译： 一种器件包括衬底和形成在衬底上并由电介质沟槽彼此隔离的多个阱。 该器件还包括形成在阱上的多个存储元件，每个存储元件大致垂直于阱延伸并且包括掺杂有n型杂质的材料。 器件还包括多个源极/漏极区域，每个源极/漏极区域形成在多个沟槽中的一个内，并且在一对存储元件之间的多个阱中的一个内部，源极/漏极区域中的每一个注入p型杂质 。 所述器件还包括形成在所述多个沟槽中的第一个沟槽中的第一衬底接触件，穿过所述衬底中的第一孔，以及形成在所述多个沟槽中的第二个沟槽中的第二衬底接触件中的第二衬底接触入第 基质。