公开(公告)号：US08598664B2

公开(公告)日：2013-12-03

申请号：US13420763

申请日：2012-03-15

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Yu Zhu

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Yu Zhu

IPC分类号： H01L27/12

CPC分类号： H01L21/28 ,  H01L29/78

摘要： Disclosed are a field effect transistor structure and a method of forming the structure. A gate stack is formed on the wafer above a designated channel region. Spacer material is deposited and anisotropically etched until just prior to exposing any horizontal surfaces of the wafer or gate stack, thereby leaving relatively thin horizontal portions of spacer material on the wafer surface and relatively thick vertical portions of spacer material on the gate sidewalls. The remaining spacer material is selectively and isotropically etched just until the horizontal portions of spacer material are completely removed, thereby leaving only the vertical portions of the spacer material on the gate sidewalls. This selective isotropic etch removes the horizontal portions of spacer material without damaging the wafer surface. Raised epitaxial source/drain regions can be formed on the undamaged wafer surface adjacent to the gate sidewall spacers in order to tailor source/drain resistance values.

摘要翻译： 公开了场效应晶体管结构和形成该结构的方法。 栅极叠层形成在指定沟道区上方的晶片上。 间隔物材料被沉积并各向异性蚀刻，直到暴露晶片或栅极堆叠的任何水平表面之前，从而在晶片表面上留下相对薄的间隔物材料的水平部分和栅极侧壁上的间隔物材料的相对较厚的垂直部分。 剩余的间隔物料被选择性地和各向同性地蚀刻，直到间隔物材料的水平部分被完全去除，从而仅留下间隔材料在浇口侧壁上的垂直部分。 该选择性各向同性蚀刻除去间隔材料的水平部分而不损坏晶片表面。 可以在与栅极侧壁间隔物相邻的未损坏的晶片表面上形成凸出的外延源极/漏极区域，以便定制源极/漏极电阻值。

公开(公告)号：US08324110B2

公开(公告)日：2012-12-04

申请号：US12698191

申请日：2010-02-02

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Yu Zhu

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Yu Zhu

IPC分类号： H01L21/461

CPC分类号： H01L21/28 ,  H01L29/78

摘要： Disclosed are a field effect transistor structure and a method of forming the structure. A gate stack is formed on the wafer above a designated channel region. Spacer material is deposited and anisotropically etched until just prior to exposing any horizontal surfaces of the wafer or gate stack, thereby leaving relatively thin horizontal portions of spacer material on the wafer surface and relatively thick vertical portions of spacer material on the gate sidewalls. The remaining spacer material is selectively and isotropically etched just until the horizontal portions of spacer material are completely removed, thereby leaving only the vertical portions of the spacer material on the gate sidewalls. This selective isotropic etch removes the horizontal portions of spacer material without damaging the wafer surface. Raised epitaxial source/drain regions can be formed on the undamaged wafer surface adjacent to the gate sidewall spacers in order to tailor source/drain resistance values.

摘要翻译： 公开了场效应晶体管结构和形成该结构的方法。 栅极叠层形成在指定沟道区上方的晶片上。 间隔物材料被沉积并各向异性蚀刻，直到暴露晶片或栅极堆叠的任何水平表面之前，从而在晶片表面上留下相对薄的间隔物材料的水平部分和栅极侧壁上的间隔物材料的相对较厚的垂直部分。 剩余的间隔物料被选择性地和各向同性地蚀刻，直到间隔物材料的水平部分被完全去除，从而仅留下间隔材料在浇口侧壁上的垂直部分。 该选择性各向同性蚀刻除去间隔材料的水平部分而不损坏晶片表面。 可以在与栅极侧壁间隔物相邻的未损坏的晶片表面上形成凸出的外延源极/漏极区域，以便定制源极/漏极电阻值。

公开(公告)号：US20120168834A1

公开(公告)日：2012-07-05

申请号：US13420763

申请日：2012-03-15

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Yu Zhu

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Yu Zhu

IPC分类号： H01L29/772

CPC分类号： H01L21/28 ,  H01L29/78

摘要： Disclosed are a field effect transistor structure and a method of forming the structure. A gate stack is formed on the wafer above a designated channel region. Spacer material is deposited and anisotropically etched until just prior to exposing any horizontal surfaces of the wafer or gate stack, thereby leaving relatively thin horizontal portions of spacer material on the wafer surface and relatively thick vertical portions of spacer material on the gate sidewalls. The remaining spacer material is selectively and isotropically etched just until the horizontal portions of spacer material are completely removed, thereby leaving only the vertical portions of the spacer material on the gate sidewalls. This selective isotropic etch removes the horizontal portions of spacer material without damaging the wafer surface. Raised epitaxial source/drain regions can be formed on the undamaged wafer surface adjacent to the gate sidewall spacers in order to tailor source/drain resistance values.

摘要翻译： 公开了场效应晶体管结构和形成该结构的方法。 栅极叠层形成在指定沟道区上方的晶片上。 间隔物材料被沉积并各向异性蚀刻，直到暴露晶片或栅极堆叠的任何水平表面之前，从而在晶片表面上留下相对薄的间隔物材料的水平部分和栅极侧壁上的间隔物材料的相对较厚的垂直部分。 剩余的间隔物料被选择性地和各向同性地蚀刻，直到间隔物材料的水平部分被完全去除，从而仅留下间隔材料在浇口侧壁上的垂直部分。 该选择性各向同性蚀刻除去间隔材料的水平部分而不损坏晶片表面。 可以在与栅极侧壁间隔物相邻的未损坏的晶片表面上形成凸出的外延源极/漏极区域，以便定制源极/漏极电阻值。

公开(公告)号：US20110186914A1

公开(公告)日：2011-08-04

申请号：US12698191

申请日：2010-02-02

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Yu Zhu

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Yu Zhu

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/336

CPC分类号： H01L21/28 ,  H01L29/78

摘要： Disclosed are a field effect transistor structure and a method of forming the structure. A gate stack is formed on the wafer above a designated channel region. Spacer material is deposited and anisotropically etched until just prior to exposing any horizontal surfaces of the wafer or gate stack, thereby leaving relatively thin horizontal portions of spacer material on the wafer surface and relatively thick vertical portions of spacer material on the gate sidewalls. The remaining spacer material is selectively and isotropically etched just until the horizontal portions of spacer material are completely removed, thereby leaving only the vertical portions of the spacer material on the gate sidewalls. This selective isotropic etch removes the horizontal portions of spacer material without damaging the wafer surface. Raised epitaxial source/drain regions can be formed on the undamaged wafer surface adjacent to the gate sidewall spacers in order to tailor source/drain resistance values.

摘要翻译： 公开了场效应晶体管结构和形成该结构的方法。 栅极叠层形成在指定沟道区上方的晶片上。 间隔物材料被沉积并各向异性蚀刻，直到暴露晶片或栅极堆叠的任何水平表面之前，从而在晶片表面上留下相对薄的间隔物材料的水平部分和栅极侧壁上的间隔物材料的相对较厚的垂直部分。 剩余的间隔物料被选择性地和各向同性地蚀刻，直到间隔物材料的水平部分被完全去除，从而仅留下间隔材料在浇口侧壁上的垂直部分。 该选择性各向同性蚀刻除去间隔材料的水平部分而不损坏晶片表面。 可以在与栅极侧壁间隔物相邻的未损坏的晶片表面上形成凸出的外延源极/漏极区域，以便定制源极/漏极电阻值。

公开(公告)号：US09054211B2

公开(公告)日：2015-06-09

申请号：US13540801

申请日：2012-07-03

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823431 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/785

摘要： An FET device structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin. The Fin-FET device channel is compressively stressed due to the pressure on the fin. A further FET device structure has Fin-FET devices in a row. An oxide element extending perpendicularly to the row of fins is abutting the fins and exerts pressure onto the fins. Device channels of the Fin-FET devices are compressively stressed due to the pressure on the fins.

摘要翻译： FET器件结构具有具有Si基材料的翅片的Fin-FET器件。 氧化物元件邻接翅片并对翅片施加压力。 Fin-FET器件通道由于鳍上的压力而受到压缩应力。 另外的FET器件结构具有Fin-FET器件。 垂直于翅片排延伸的氧化物元件邻接散热片并对翅片施加压力。 Fin-FET器件的器件通道由于鳍片上的压力而受到压缩应力。

公开(公告)号：US08994085B2

公开(公告)日：2015-03-31

申请号：US13551714

申请日：2012-07-18

申请人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Terence B. Hook ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Tenko Yamashita ,  Chun-Chen Yeh

发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Terence B. Hook ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L21/84 ,  H01L27/11 ,  H01L27/12

CPC分类号： H01L21/84 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/1203 ,  H01L29/945

摘要： An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.

摘要翻译： 一种集成电路，包括N +型层，设置在N +型层上的缓冲层; 形成在缓冲层上的P型区域; 覆盖N +型层的绝缘体层，覆盖绝缘体层的硅层，形成在硅层中并与延伸到N +型层的沟槽电容器的导电节点连接的嵌入式RAM FET，N +型层形成 沟槽电容器的平板电极，通过硅层和绝缘层的第一接触并且电连接到N +型层，形成在P型区域上方的硅层中的第一逻辑RAM FET，P型区域用作 第一逻辑RAM FET的P型背栅，以及通过硅层和绝缘层的第二接触，并且电连接到P型区域。

公开(公告)号：US08710588B2

公开(公告)日：2014-04-29

申请号：US13595025

申请日：2012-08-27

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Dechao Guo ,  Pranita Kulkarni ,  Philip J. Oldiges ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Dechao Guo ,  Pranita Kulkarni ,  Philip J. Oldiges ,  Ghavam G. Shahidi

IPC分类号： H01L27/12

CPC分类号： H01L29/66636 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78654

摘要： A semiconductor device and a method of fabricating a semiconductor device are disclosed. In one embodiment, the method comprises providing a semiconductor substrate, epitaxially growing a Ge layer on the substrate, and epitaxially growing a semiconductor layer on the Ge layer, where the semiconductor layer has a thickness of 10 nm or less. This method further comprises removing at least a portion of the Ge layer to form a void beneath the Si layer, and filling the void at least partially with a dielectric material. In this way, the semiconductor layer becomes an extremely thin semiconductor-on-insulator layer. In one embodiment, after the void is filled with the dielectric material, in-situ doped source and drain regions are grown on the semiconductor layer. In one embodiment, the method further comprises annealing said source and drain regions to form doped extension regions in the semiconductor layer.

摘要翻译： 公开了半导体器件和制造半导体器件的方法。 在一个实施例中，该方法包括提供半导体衬底，在衬底上外延生长Ge层，并在Ge层上外延生长半导体层，其中半导体层的厚度为10nm或更小。 该方法还包括去除Ge层的至少一部分以在Si层下形成空隙，并且至少部分地用电介质材料填充空隙。 以这种方式，半导体层成为非常薄的绝缘体上半导体层。 在一个实施例中，在空隙填充有电介质材料之后，在半导体层上生长原位掺杂的源极和漏极区。 在一个实施例中，该方法还包括退火所述源区和漏区以在半导体层中形成掺杂的延伸区。

公开(公告)号：US08653596B2

公开(公告)日：2014-02-18

申请号：US13344885

申请日：2012-01-06

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Terence B. Hook ,  Ali Khakifirooz ,  Pranita Kulkarni

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Terence B. Hook ,  Ali Khakifirooz ,  Pranita Kulkarni

IPC分类号： H01L21/70 ,  H01L27/12 ,  H01L21/762 ,  H01L21/84

CPC分类号： H01L29/945 ,  H01L21/84 ,  H01L27/1052 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/1116 ,  H01L27/1203 ,  H01L27/1207

摘要： An integrated circuit includes an SOI substrate with a unitary N+ layer below the BOX, a P region in the N+ layer, an eDRAM with an N+ plate, and logic/SRAM devices above the P region. The P region functions as a back gate of the logic/SRAM devices. An optional intrinsic (undoped) layer can be formed between the P back gate layer and the N+ layer to reduce the junction field and lower the junction leakage between the P back gate and the N+ layer. In another embodiment an N or N+ back gate can be formed in the P region. The N+ back gate functions as a second back gate of the logic/SRAM devices. The N+ plate of the SOI eDRAM, the P back gate, and the N+ back gate can be electrically biased at the same or different voltage potentials. Methods to fabricate the integrated circuits are also disclosed.

摘要翻译： 集成电路包括在BOX下方具有单一N +层的SOI衬底，N +层中的P区，N +板的eDRAM和P区上方的逻辑/ SRAM器件。 P区域用作逻辑/ SRAM器件的后门。 可以在P背栅层和N +层之间形成可选的本征（未掺杂）层，以减少结场并降低P背栅与N +层之间的结泄漏。 在另一个实施例中，可以在P区中形成N或N +背栅。 N +后门作为逻辑/ SRAM器件的第二个后门。 SOI eDRAM的N +板，P背栅极和N +背栅极可以在相同或不同的电压电位下被电偏置。 还公开了制造集成电路的方法。

公开(公告)号：US20140024215A1

公开(公告)日：2014-01-23

申请号：US13555306

申请日：2012-07-23

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Ying Zhang

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Ying Zhang

IPC分类号： B44C1/22 ,  H01B13/00 ,  H01L21/308

CPC分类号： H01L21/3086 ,  H01B13/00 ,  H01B19/04 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/32134 ,  H01L21/32137

摘要： Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography effects seen in prior art double patterning techniques by ensuring that the substrate itself is only subjected to a single etch process. Specifically, in the method, a first mask layer is formed on the substrate and processed such that it has a doped region and multiple undoped regions within the doped region. Then, either the undoped regions or the doped region can be selectively removed in order to form a mask pattern above the substrate. Once the mask pattern is formed, an etch process can be performed to transfer the mask pattern into the substrate. Depending upon whether the undoped regions are removed or the doped region is removed, the mask pattern will form openings (e.g., vias or trenches) or mesas, respectively, on the substrate.

摘要翻译： 公开了一种用于在基板上形成开口（例如，通孔或沟槽）或台面的改进的双重图案化方法。 该方法通过确保衬底本身仅经历单次蚀刻工艺来避免现有技术的双重图案化技术中所见到的晶片形貌效应。 具体地说，在该方法中，在衬底上形成第一掩模层并进行处理，使得其在掺杂区域内具有掺杂区域和多个未掺杂区域。 然后，可以选择性地去除未掺杂区域或掺杂区域，以在衬底上方形成掩模图案。 一旦形成掩模图案，就可以执行蚀刻工艺以将掩模图案转印到基板中。 取决于未掺杂的区域是去除还是去除掺杂区域，掩模图案将分别在衬底上形成开口（例如，通孔或沟槽）或台面。

公开(公告)号：US20140024191A1

公开(公告)日：2014-01-23

申请号：US13555240

申请日：2012-07-23

申请人： Kuang-Jung Chen ,  Kangguo Cheng ,  Bruce B. Doris ,  Steven J. Holmes ,  Sen Liu

发明人： Kuang-Jung Chen ,  Kangguo Cheng ,  Bruce B. Doris ,  Steven J. Holmes ,  Sen Liu

IPC分类号： H01L21/31 ,  H01L21/336

CPC分类号： H01L21/0274 ,  H01L21/26586 ,  H01L21/3081 ,  H01L21/76229 ,  H01L21/76283 ,  H01L29/517 ,  H01L29/66575 ,  H01L29/78

摘要： A method of forming different structures of a semiconductor device using a single mask and a hybrid photoresist. The method includes: applying a first photoresist layer on a semiconductor substrate; patterning the first photoresist layer using a photomask to form a first patterned photoresist layer; using the first patterned photoresist layer to form a first structure of a semiconductor device; removing the first patterned photoresist layer; applying a second photoresist layer on the semiconductor substrate; patterning the second photoresist layer using the photomask to form a second patterned photoresist layer; using the second patterned photoresist layer to form a second structure of a semiconductor device; removing the second patterned photoresist layer; and wherein either the first or the second photoresist layer is a hybrid photoresist layer comprising a hybrid photoresist.

摘要翻译： 使用单个掩模和混合光致抗蚀剂形成半导体器件的不同结构的方法。 该方法包括：在半导体衬底上施加第一光致抗蚀剂层; 使用光掩模图案化第一光致抗蚀剂层以形成第一图案化光致抗蚀剂层; 使用所述第一图案化的光致抗蚀剂层形成半导体器件的第一结构; 去除第一图案化光致抗蚀剂层; 在所述半导体衬底上施加第二光致抗蚀剂层; 使用光掩模图案化第二光致抗蚀剂层以形成第二图案化光致抗蚀剂层; 使用所述第二图案化的光致抗蚀剂层形成半导体器件的第二结构; 去除第二图案化光致抗蚀剂层; 并且其中所述第一或第二光致抗蚀剂层是包含混合光致抗蚀剂的混合光致抗蚀剂层。