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    Amidine derivatives and drug carriers comprising the same
    1.
    发明授权
    Amidine derivatives and drug carriers comprising the same 有权
    脒衍生物和包含其的药物载体

    公开(公告)号：US06228391B1

    公开(公告)日：2001-05-08

    申请号：US09202193

    申请日：1998-12-10

    Applicant: Kazuhiro Shimizu ,  Masashi Isozaki ,  Kazunori Koiwai

    Inventor： Kazuhiro Shimizu ,  Masashi Isozaki ,  Kazunori Koiwai

    IPC: C07C25714

    CPC classification number: C07C257/18 ,  A61K9/1272 ,  C07C257/14 ,  C07C335/32 ,  C07C335/36

    Abstract: Novel amidine derivatives of the formula (1); and drug carriers such as liposomes or emulsions comprising the derivatives, which can enclose genetic materials or drugs and transfer them to cells or affected sites efficiently and safely, wherein A is an aromatic ring, R1 and R2 are the same or different and independently represent an alkyl group having any one of 10 to 25 carbon atoms, and an alkenyl group having any one of 10 to 25 carbon atoms, X and Y are the same or different and independently represent —O—, —S—, —COO—, —OCO—, —CONH—, or —NHCO—, m is 0 or 1, and n is 0 or a natural number of 1 to 6.

    Abstract translation: 式（1）的新型脒衍生物; 和药物载体如脂质体或包含衍生物的乳剂，其可以包裹遗传材料或药物并且有效和安全地将它们转移到细胞或受影响的位点，其中A是芳环，R 1和R 2相同或不同并且独立地表示 具有10至25个碳原子的任何一个的烷基和具有10至25个碳原子的任何一个的烯基可以相同或不同并且独立地表示-O - ， - S - ， - COO - ， - OCO-，-CONH-或-NHCO-，m为0或1，n为0或自然数为1至6。

    Semiconductor device
    5.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07977787B2

    公开(公告)日：2011-07-12

    申请号：US12332409

    申请日：2008-12-11

    Applicant: Kazuhiro Shimizu ,  Hajime Akiyama ,  Naoki Yasuda

    Inventor： Kazuhiro Shimizu ,  Hajime Akiyama ,  Naoki Yasuda

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC classification number: H01L21/67271 ,  H01L21/67282 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.

    Abstract translation: 半导体器件制造装置具备：具有喷射导电性溶剂的印刷头，绝缘性溶剂和界面处理液的图形印刷部。 打印头形成为使得可以基于来自晶片测试部件的绘图图案的信息，从存储部分获得关于晶片的信息和来自芯片坐标识别部分的坐标信息，将期望的电路图形图案印刷在晶片上 。 在根据本发明的半导体器件制造方法中，通过使用半导体器件制造设备以通过印刷处理形成期望的电路的方式制造半导体器件。 在半导体器件中，焊盘电极等以能够通过打印电路图形进行修整处理的方式形成。

    Nonvolatile semiconductor memory device
    6.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US07786525B2

    公开(公告)日：2010-08-31

    申请号：US12104945

    申请日：2008-04-17

    Applicant: Kazuhiro Shimizu

    Inventor： Kazuhiro Shimizu

    IPC: H01L29/788

    CPC classification number: H01L29/7883 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42336

    Abstract: A nonvolatile semiconductor memory device includes an element isolation insulating film buried in first trenches, a floating gate electrode formed on an element forming region with a first gate insulating film being interposed between them, and a second gate insulating film formed on upper portions of the floating gate electrode and an element isolation insulating film. The floating gate electrode is formed so as to have a side that extends from a bottom thereof to its upper portion and is substantially an extension of a sidewall of each first trench. The element isolation insulating film includes a portion located between its sidewall and the sidewall of a second trench, and the portion of the element isolation insulating film having a film thickness in a direction along the upper surface of the semiconductor substrate. The film thickness is equal to a film thickness of the second gate insulating film.

    Abstract translation: 非易失性半导体存储器件包括埋在第一沟槽中的元件隔离绝缘膜，形成在元件形成区域上的浮置栅极，第一栅极绝缘膜介于其间;以及第二栅极绝缘膜，形成在浮置的上部 栅电极和元件隔离绝缘膜。 浮栅电极形成为具有从其底部延伸到其上部并且基本上是每个第一沟槽的侧壁的延伸部的侧面。 元件隔离绝缘膜包括位于其侧壁和第二沟槽的侧壁之间的部分，元件隔离绝缘膜的沿着半导体衬底的上表面的方向具有膜厚度的部分。 膜厚度等于第二栅极绝缘膜的膜厚度。

    Powder-Containing Transparent Solid Cosmetic Preparation
    7.
    发明申请
    Powder-Containing Transparent Solid Cosmetic Preparation 审中-公开
    含粉末透明固体化妆品制备

    公开(公告)号：US20090053269A1

    公开(公告)日：2009-02-26

    申请号：US11887369

    申请日：2006-09-07

    Applicant: Kazuhiro Shimizu

    Inventor： Kazuhiro Shimizu

    IPC: A61K8/89 ,  A61K8/72

    CPC classification number: A61K8/891 ,  A61K8/02 ,  A61K8/022 ,  A61K8/0241 ,  A61K8/11 ,  A61K2800/262 ,  A61K2800/412 ,  A61K2800/622 ,  A61K2800/624 ,  A61K2800/654 ,  A61Q1/02 ,  A61Q1/08 ,  A61Q1/10 ,  A61Q1/12

    Abstract: The present invention provides a novel solid powder which has transparency in its appearance, and has excellent usability and, in addition, excellent feeling of use such as dry feeling and fresh light feeling without sticky feeling during application. It is achieved by a solid powder cosmetic comprising: (A) 25 to 55% by mass of elastic powder mixture; (B) 20 to 40% by mass of non-elastic spherical silicone resin powder with an average particle diameter within the range of 0.1 to 50 μm; and (C) 25 to 55% by mass of oil, as essential components, wherein (A) the elastic powder mixture comprises one or more types of each (A1) an elastic powder and (A2) a composite powder obtained by coating the periphery of an elastic powder with a non-elastic material, said solid powder cosmetic being obtained by caking a mixed composition of these essential components.

    Abstract translation: 本发明提供了一种外观透明的新型固体粉末，其使用性优异，并且在使用时具有优良的使用感，如干燥感和新鲜感觉，无粘性。 其通过固体粉末化妆品实现，其包含：（A）25〜55质量％的弹性粉末混合物; （B）20〜40质量％的平均粒径为0.1〜50μm的非弹性球形的有机硅树脂粉末; 和（C）25〜55质量％的油作为必要成分，其中（A）弹性粉末混合物包含一种或多种（A1）弹性粉末和（A2）通过涂覆周边 具有非弹性材料的弹性粉末，所述固体粉末化妆品通过粘结这些基本组分的混合组合物而获得。

    Semiconductor device with improved resurf features including trench isolation structure
    9.
    发明授权
    Semiconductor device with improved resurf features including trench isolation structure 有权
    具有改进的复现特征的半导体器件包括沟槽隔离结构

    公开(公告)号：US07294901B2

    公开(公告)日：2007-11-13

    申请号：US10761235

    申请日：2004-01-22

    Applicant: Kazuhiro Shimizu

    Inventor： Kazuhiro Shimizu

    IPC: H01L23/58

    CPC classification number: H01L29/7816 ,  H01L21/763 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/7801 ,  H01L29/7823 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A p impurity region (3) defines a RESURF isolation region in an n− semiconductor layer (2). A trench isolation structure (8a) and the p impurity region (3) together define a trench isolation region in the n− semiconductor layer (2) in the RESURF isolation region. An nMOS transistor (103) is provided in the trench isolation region. A control circuit is provided in the RESURF isolation region excluding the trench isolation region. An n+ buried impurity region (4) is provided at the interface between the n− semiconductor layer (2) and a p− semiconductor substrate (1), and under an n+ impurity region 7 connected to a drain electrode (14) of the nMOS transistor (103).

    Abstract translation: p杂质区（3）在n + - 半导体层（2）中限定了RESURF隔离区。 沟槽隔离结构（8a）和p杂质区（3）共同限定了RESURF隔离区中的n + - 半导体层（2）中的沟槽隔离区。 nMOS晶体管（103）设置在沟槽隔离区域中。 在除了沟槽隔离区域之外的RESURF隔离区域中提供控制电路。 在n + - 半导体层（2）和半导体衬底（2）之间的界面处设置有n + + / / 1），以及连接到nMOS晶体管（103）的漏电极（14）的n + H + +杂质区域7。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    10.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20070187798A1

    公开(公告)日：2007-08-16

    申请号：US11611493

    申请日：2006-12-15

    Applicant: Satoshi RITTAKU ,  Kazuhiro Shimizu

    Inventor： Satoshi RITTAKU ,  Kazuhiro Shimizu

    IPC: H01L21/336 ,  H01L29/00

    CPC classification number: H01L21/823857 ,  H01L21/823462 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/66681

    Abstract: A semiconductor device including a high voltage element and a low voltage element, including: a semiconductor substrate having high voltage element region where the high voltage element is formed, and a low voltage element region where the low voltage element is formed; a first LOCOS isolation structure disposed in the high voltage element region; and a second LOCOS isolation structure disposed in the low voltage element region, wherein the first LOCOS isolation structure includes a LOCOS oxide film formed on a surface of the semiconductor substrate and a CVD oxide film formed on the LOCOS oxide film, and the second LOCOS isolation structure includes a LOCOS oxide film.

    Abstract translation: 一种包括高电压元件和低电压元件的半导体器件，包括：具有形成高电压元件的高电压元件区域的半导体衬底和形成低电压元件的低电压元件区域; 设置在所述高电压元件区域中的第一LOCOS隔离结构; 以及设置在所述低电压元件区域中的第二LOCOS隔离结构，其中所述第一LOCOS隔离结构包括形成在所述半导体衬底的表面上的LOCOS氧化物膜和形成在所述LOCOS氧化物膜上的CVD氧化膜，以及所述第二LOCOS隔离 结构包括LOCOS氧化物膜。

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