公开(公告)号：US5287284A

公开(公告)日：1994-02-15

申请号：US792160

申请日：1991-11-14

申请人： Kazuhiro Sugino ,  Shingo Akasaka ,  Hiroko Imanishi ,  Junichi Saeki ,  Kunihiko Nishi ,  Asao Nishimura

发明人： Kazuhiro Sugino ,  Shingo Akasaka ,  Hiroko Imanishi ,  Junichi Saeki ,  Kunihiko Nishi ,  Asao Nishimura

IPC分类号： G06F17/50 ,  G06Q10/06 ,  G06Q10/08 ,  G06F15/46

CPC分类号： G06Q10/06 ,  G06F17/50 ,  G06Q10/087

摘要： A product specification complex analysis system is provided which inputs product specifications of an external form and materials, design parameters determined by analysis and evaluation in the specifications, the range of the change of the parameters and a plurality of items of estimates as external input data, calls out and executes an evaluation program corresponding to each item of the estimates and stored in advance, from a group of evaluation programs whenever the item of the estimates is renewed, in order to sequentially evaluate the product specifications for each item of the estimates, determines the fluctuation of analysis results with respect to the change of the design parameters within designated ranges of changes, evaluates trade-off between the analysis results by changing the design parameters from the analysis results corresponding to the items of the estimates so as to make maximal evaluation values in an evaluation formula as an estimate function with weights comprising each of these analysis results, and can thus obtain optimum design parameters.

摘要翻译： 提供了一种产品规格复杂分析系统，其输入外部形式和材料的产品规格，通过规格中的分析和评估确定的设计参数，参数变化的范围和多个估计项作为外部输入数据， 呼叫并执行与估计的每个项目相对应的评估程序，并且每当估计的项目被更新时，从一组评估程序预先存储，以便依次评估估计的每个项目的产品规格，确定 关于设计参数在指定变化范围内变化的分析结果的波动，通过从与估计项目相对应的分析结果中改变设计参数来评估分析结果之间的权衡，以便进行最大评估 评估公式中的值作为具有权重的估计函数 分析这些分析结果，从而获得最佳的设计参数。

公开(公告)号：US5572430A

公开(公告)日：1996-11-05

申请号：US905888

申请日：1992-06-29

申请人： Shingo Akasaka ,  Sugino Kazuhiro ,  Hiroko Imanishi ,  Junichi Saeki ,  Kunihiko Nishi

发明人： Shingo Akasaka ,  Sugino Kazuhiro ,  Hiroko Imanishi ,  Junichi Saeki ,  Kunihiko Nishi

IPC分类号： G06F17/50 ,  G06F19/00

CPC分类号： G06F17/50

摘要： In order to derive optimum design specifications based on total evaluation performed on a product as a whole instead of individual design items during a process of determining design specifications involving a plurality of design items, candidates for the product specifications are selected by controlling design parameters for each of the design items in an integrated manner, computing values of a plurality of evaluation items evaluating candidates for the design specifications and performing total evaluation on all the evaluation items based on their computed values through collaboration among a plurality of design sections altogether auto-correcting all relevant design parameters quickly and relaxing as well as reassessing design constraints for a design parameter.

摘要翻译： 为了在确定涉及多个设计项目的设计规范的过程中基于在整个产品上执行的总体评估而不是单独的设计项目来获得最佳设计规范，通过控制每个设计参数的选择来选择产品规格的候选 以综合方式计算设计项目，计算评估设计规范的候选者的多个评估项目的值，并且通过多个设计部分之间的协作，基于它们的计算值对所有评估项目进行总体评估，全部自动校正所有 相关设计参数快速轻松，并重新设计设计参数的约束。

公开(公告)号：US4989166A

公开(公告)日：1991-01-29

申请号：US340480

申请日：1989-04-19

申请人： Shingo Akasaka ,  Kazuhiro Sugino ,  Junichi Saeki ,  Kunihiko Nishi ,  Hisashi Onari

发明人： Shingo Akasaka ,  Kazuhiro Sugino ,  Junichi Saeki ,  Kunihiko Nishi ,  Hisashi Onari

IPC分类号： B29C33/38 ,  B29C45/76 ,  G06F17/50 ,  G06T17/00

CPC分类号： G06T17/00 ,  B29C33/3835 ,  B29C45/76 ,  G06F17/5018 ,  G06F2217/16 ,  G06F2217/41

摘要： The present invention is applied to the design of a mold for a semiconductor or the like and provides a method for synthesizing analysis models, in which analysis programs corresponding to shapes and features of an object to be analyzed are registered in advance in a numerical analysis system, the analysis programs are made to correspond to partial shapes divided according to the shapes and features of the object to be analyzed and are partially modelled, whereas input and output items between adjacent portions are controlled on the basis of the positional relationship between the portions and input and output information of the analysis programs placed in correspondence to the portions. The invention further provides a flow analysis system for computing a flow state of material to evaluate a shape of a flowpassage, a flow control condition, material and the like, the system comprising input means for inputting a flowpassage shape of a mold, properties of material and flow control conditions, model synthesizing means for extracting a feature of the flowpassage shape, judging an adaptability with the already registered analysis model from the extracted features and synthesizing flow analysis models capable of analyzing the entire flowpassage, and program execution means for removing programs corresponding to the synthesized model to sequentially execute them.

公开(公告)号：US6124629A

公开(公告)日：2000-09-26

申请号：US168097

申请日：1998-10-08

申请人： Gen Murakami ,  Kunihiro Tsubosaki ,  Masahiro Ichitani ,  Kunihiko Nishi ,  Ichiro Anjo ,  Asao Nishimura ,  Makoto Kitano ,  Akihiro Yaguchi ,  Sueo Kawai ,  Masatsugu Ogata ,  Syuuji Eguchi ,  Hiroyoshi Kokaku ,  Masanori Segawa ,  Hiroshi Hozoji ,  Takashi Yokoyama ,  Noriyuki Kinjo ,  Aizo Kaneda ,  Junichi Saeki ,  Shozo Nakamura ,  Akio Hasebe ,  Hiroshi Kikuchi ,  Isamu Yoshida ,  Takashi Yamazaki ,  Kazuyoshi Oshima ,  Tetsuro Matsumoto

发明人： Gen Murakami ,  Kunihiro Tsubosaki ,  Masahiro Ichitani ,  Kunihiko Nishi ,  Ichiro Anjo ,  Asao Nishimura ,  Makoto Kitano ,  Akihiro Yaguchi ,  Sueo Kawai ,  Masatsugu Ogata ,  Syuuji Eguchi ,  Hiroyoshi Kokaku ,  Masanori Segawa ,  Hiroshi Hozoji ,  Takashi Yokoyama ,  Noriyuki Kinjo ,  Aizo Kaneda ,  Junichi Saeki ,  Shozo Nakamura ,  Akio Hasebe ,  Hiroshi Kikuchi ,  Isamu Yoshida ,  Takashi Yamazaki ,  Kazuyoshi Oshima ,  Tetsuro Matsumoto

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/31 ,  H01L23/495 ,  H01L25/10 ,  H01L29/06 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34

CPC分类号： H01L24/32 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49555 ,  H01L23/49558 ,  H01L23/49568 ,  H01L23/49586 ,  H01L24/05 ,  H01L24/06 ,  H01L25/105 ,  H01L29/0657 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/06136 ,  H01L2224/16 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48799 ,  H01L2224/73215 ,  H01L2224/85205 ,  H01L2224/8592 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01092 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/144 ,  H05K1/181 ,  H05K3/3421 ,  Y10T29/49121

摘要： As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

摘要翻译： 由于半导体芯片尺寸大，高集成度和加速度，所以难以将半导体芯片与包装中的引线组合在一起。 鉴于这种困难，已经采用称为半导体和引线堆叠和封装的称为“片上引线”或“引线芯片”结构的封装结构。 在该结构的封装中，根据本发明，内引线和半导体芯片的前端部之间的间隙比除引导端部和半导体芯片之外的内引线部分之间的间隙宽，从而减小 杂散容量，提高信号传输速率和减少电气噪声。

公开(公告)号：US6100115A

公开(公告)日：2000-08-08

申请号：US166121

申请日：1998-10-05

申请人： Gen Murakami ,  Kunihiro Tsubosaki ,  Masahiro Ichitani ,  Kunihiko Nishi ,  Ichiro Anjo ,  Asao Nishimura ,  Makoto Kitano ,  Akihiro Yaguchi ,  Sueo Kawai ,  Masatsugu Ogata ,  Syuuji Eguchi ,  Hiroyoshi Kokaku ,  Masanori Segawa ,  Hiroshi Hozoji ,  Takashi Yokoyama ,  Noriyuki Kinjo ,  Aizo Kaneda ,  Junichi Saeki ,  Shozo Nakamura ,  Akio Hasebe ,  Hiroshi Kikuchi ,  Isamu Yoshida ,  Takashi Yamazaki ,  Kazuyoshi Oshima ,  Tetsuro Matsumoto

发明人： Gen Murakami ,  Kunihiro Tsubosaki ,  Masahiro Ichitani ,  Kunihiko Nishi ,  Ichiro Anjo ,  Asao Nishimura ,  Makoto Kitano ,  Akihiro Yaguchi ,  Sueo Kawai ,  Masatsugu Ogata ,  Syuuji Eguchi ,  Hiroyoshi Kokaku ,  Masanori Segawa ,  Hiroshi Hozoji ,  Takashi Yokoyama ,  Noriyuki Kinjo ,  Aizo Kaneda ,  Junichi Saeki ,  Shozo Nakamura ,  Akio Hasebe ,  Hiroshi Kikuchi ,  Isamu Yoshida ,  Takashi Yamazaki ,  Kazuyoshi Oshima ,  Tetsuro Matsumoto

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/31 ,  H01L23/495 ,  H01L25/10 ,  H01L29/06 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34

CPC分类号： H01L24/32 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49555 ,  H01L23/49558 ,  H01L23/49568 ,  H01L23/49586 ,  H01L24/05 ,  H01L24/06 ,  H01L25/105 ,  H01L29/0657 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/06136 ,  H01L2224/16 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48799 ,  H01L2224/73215 ,  H01L2224/85205 ,  H01L2224/8592 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01092 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/144 ,  H05K1/181 ,  H05K3/3421 ,  Y10T29/49121

摘要： As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

公开(公告)号：US06531760B1

公开(公告)日：2003-03-11

申请号：US09558105

申请日：2000-04-25

申请人： Gen Murakami ,  Kunihiro Tsubosaki ,  Masahiro Ichitani ,  Kunihiko Nishi ,  Ichiro Anjo ,  Asao Nishimura ,  Makoto Kitano ,  Akihiro Yaguchi ,  Sueo Kawai ,  Masatsugu Ogata ,  Syuuji Eguchi ,  Hiroyoshi Kokaku ,  Masanori Segawa ,  Hiroshi Hozoji ,  Takashi Yokoyama ,  Noriyuki Kinjo ,  Aizo Kaneda ,  Junichi Saeki ,  Shozo Nakamura ,  Akio Hasebe ,  Hiroshi Kikuchi ,  Isamu Yoshida ,  Takashi Yamazaki ,  Kazuyoshi Oshima ,  Tetsuro Matsumoto

发明人： Gen Murakami ,  Kunihiro Tsubosaki ,  Masahiro Ichitani ,  Kunihiko Nishi ,  Ichiro Anjo ,  Asao Nishimura ,  Makoto Kitano ,  Akihiro Yaguchi ,  Sueo Kawai ,  Masatsugu Ogata ,  Syuuji Eguchi ,  Hiroyoshi Kokaku ,  Masanori Segawa ,  Hiroshi Hozoji ,  Takashi Yokoyama ,  Noriyuki Kinjo ,  Aizo Kaneda ,  Junichi Saeki ,  Shozo Nakamura ,  Akio Hasebe ,  Hiroshi Kikuchi ,  Isamu Yoshida ,  Takashi Yamazaki ,  Kazuyoshi Oshima ,  Tetsuro Matsumoto

IPC分类号： H01L23495

CPC分类号： H01L23/3107 ,  H01L23/4951 ,  H01L23/49555 ,  H01L23/49558 ,  H01L23/49568 ,  H01L23/49586 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/105 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/16245 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48799 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85205 ,  H01L2224/8592 ,  H01L2224/92147 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01092 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/144 ,  H05K1/181 ,  H05K3/3421 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/3512 ,  H01L2924/0695 ,  H01L2224/85399

摘要： As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

公开(公告)号：US6072231A

公开(公告)日：2000-06-06

申请号：US066877

申请日：1998-04-28

申请人： Gen Murakami ,  Kunihiro Tsubosaki ,  Masahiro Ichitani ,  Kunihiko Nishi ,  Ichiro Anjoh ,  Asao Nishimura ,  Makoto Kitano ,  Akihiro Yaguchi ,  Sueo Kawai ,  Masatsugu Ogata ,  Syuuji Eguchi ,  Hiroyoshi Kokaku ,  Masanori Segawa ,  Hiroshi Hozoji ,  Takashi Yokoyama ,  Noriyuki Kinjo ,  Aizo Kaneda ,  Junichi Saeki ,  Shozo Nakamura ,  Akio Hasebe ,  Hiroshi Kikuchi ,  Isamu Yoshida ,  Takashi Yamazaki ,  Kazuyoshi Oshima ,  Tetsurou Matsumoto

发明人： Gen Murakami ,  Kunihiro Tsubosaki ,  Masahiro Ichitani ,  Kunihiko Nishi ,  Ichiro Anjoh ,  Asao Nishimura ,  Makoto Kitano ,  Akihiro Yaguchi ,  Sueo Kawai ,  Masatsugu Ogata ,  Syuuji Eguchi ,  Hiroyoshi Kokaku ,  Masanori Segawa ,  Hiroshi Hozoji ,  Takashi Yokoyama ,  Noriyuki Kinjo ,  Aizo Kaneda ,  Junichi Saeki ,  Shozo Nakamura ,  Akio Hasebe ,  Hiroshi Kikuchi ,  Isamu Yoshida ,  Takashi Yamazaki ,  Kazuyoshi Oshima ,  Tetsurou Matsumoto

IPC分类号： H01L21/52 ,  H01L23/31 ,  H01L23/495 ,  H01L23/50 ,  H01L25/10 ,  H01L29/06 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34

CPC分类号： H01L23/3107 ,  H01L23/4951 ,  H01L23/49555 ,  H01L23/49558 ,  H01L23/49568 ,  H01L23/49586 ,  H01L24/32 ,  H01L24/49 ,  H01L25/105 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/16245 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48799 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85205 ,  H01L2224/8592 ,  H01L2224/92147 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01092 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/144 ,  H05K1/181 ,  H05K3/3421

摘要： As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

公开(公告)号：US5914530A

公开(公告)日：1999-06-22

申请号：US52981

申请日：1998-04-01

申请人： Gen Murakami ,  Kunihiro Tsubosaki ,  Masahiro Ichitani ,  Kunihiko Nishi ,  Ichiro Anjoh ,  Asao Nishimura ,  Makoto Kitano ,  Akihiro Yaguchi ,  Sueo Kawai ,  Masatsugu Ogata ,  Syuuji Eguchi ,  Hiroyoshi Kokaku ,  Masanori Segawa ,  Hiroshi Hozoji ,  Takashi Yokoyama ,  Noriyuki Kinjo ,  Aizo Kaneda ,  Junichi Saeki ,  Shozo Nakamura ,  Akio Hasebe ,  Hiroshi Kikuchi ,  Isamu Yoshida ,  Takashi Yamazaki ,  Kazuyoshi Oshima ,  Tetsuro Matsumoto

发明人： Gen Murakami ,  Kunihiro Tsubosaki ,  Masahiro Ichitani ,  Kunihiko Nishi ,  Ichiro Anjoh ,  Asao Nishimura ,  Makoto Kitano ,  Akihiro Yaguchi ,  Sueo Kawai ,  Masatsugu Ogata ,  Syuuji Eguchi ,  Hiroyoshi Kokaku ,  Masanori Segawa ,  Hiroshi Hozoji ,  Takashi Yokoyama ,  Noriyuki Kinjo ,  Aizo Kaneda ,  Junichi Saeki ,  Shozo Nakamura ,  Akio Hasebe ,  Hiroshi Kikuchi ,  Isamu Yoshida ,  Takashi Yamazaki ,  Kazuyoshi Oshima ,  Tetsuro Matsumoto

IPC分类号： H01L21/52 ,  H01L23/31 ,  H01L23/495 ,  H01L23/50 ,  H01L25/10 ,  H01L29/06 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34

CPC分类号： H01L23/3107 ,  H01L23/4951 ,  H01L23/49555 ,  H01L23/49558 ,  H01L23/49568 ,  H01L23/49586 ,  H01L24/32 ,  H01L24/49 ,  H01L25/105 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/16245 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48799 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85205 ,  H01L2224/8592 ,  H01L2224/92147 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01092 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/144 ,  H05K1/181 ,  H05K3/3421

摘要： As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

公开(公告)号：US5612569A

公开(公告)日：1997-03-18

申请号：US464131

申请日：1995-06-05

申请人： Gen Murakami ,  Kunihiro Tsubosaki ,  Masahiro Ichitani ,  Kunihiko Nishi ,  Ichiro Anjoh ,  Asao Nishimura ,  Makoto Kitano ,  Akihiro Yaguchi ,  Sueo Kawai ,  Masatsugu Ogata ,  Syuuji Eguchi ,  Hiroyoshi Kokaku ,  Masanori Segawa ,  Hiroshi Hozoji ,  Takashi Yokoyama ,  Noriyuki Kinjo ,  Aizo Kaneda ,  Junichi Saeki ,  Shozo Nakamura ,  Akio Hasebe ,  Hiroshi Kikuchi ,  Isamu Yoshida ,  Takashi Yamazaki ,  Kazuyoshi Oshima ,  Tetsurou Matsumoto

发明人： Gen Murakami ,  Kunihiro Tsubosaki ,  Masahiro Ichitani ,  Kunihiko Nishi ,  Ichiro Anjoh ,  Asao Nishimura ,  Makoto Kitano ,  Akihiro Yaguchi ,  Sueo Kawai ,  Masatsugu Ogata ,  Syuuji Eguchi ,  Hiroyoshi Kokaku ,  Masanori Segawa ,  Hiroshi Hozoji ,  Takashi Yokoyama ,  Noriyuki Kinjo ,  Aizo Kaneda ,  Junichi Saeki ,  Shozo Nakamura ,  Akio Hasebe ,  Hiroshi Kikuchi ,  Isamu Yoshida ,  Takashi Yamazaki ,  Kazuyoshi Oshima ,  Tetsurou Matsumoto

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/31 ,  H01L23/495 ,  H01L25/10 ,  H01L29/06 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/32 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49555 ,  H01L23/49558 ,  H01L23/49568 ,  H01L23/49586 ,  H01L24/05 ,  H01L24/06 ,  H01L25/105 ,  H01L29/0657 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/06136 ,  H01L2224/16 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48799 ,  H01L2224/73215 ,  H01L2224/85205 ,  H01L2224/8592 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01092 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/144 ,  H05K1/181 ,  H05K3/3421 ,  Y10T29/49121

摘要： As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

摘要翻译： 由于半导体芯片尺寸大，高集成度和加速度，所以难以将半导体芯片与包装中的引线组合在一起。 鉴于这种困难，已经采用称为半导体和引线堆叠和封装的称为“片上引线”或“引线芯片”结构的封装结构。 在该结构的封装中，根据本发明，内引线和半导体芯片的前端部之间的间隙比除引导端部和半导体芯片之外的内引线部分之间的间隙宽，从而减小 杂散容量，提高信号传输速率和减少电气噪声。

公开(公告)号：US06720208B2

公开(公告)日：2004-04-13

申请号：US10322672

申请日：2002-12-19

申请人： Gen Murakami ,  Kunihiro Tsubosaki ,  Masahiro Ichitani ,  Kunihiko Nishi ,  Ichiro Anjo ,  Asao Nishimura ,  Makoto Kitano ,  Akihiro Yaguchi ,  Sueo Kawai ,  Masatsugu Ogata ,  Syuuji Eguchi ,  Hiroyoshi Kokaku ,  Masanori Segawa ,  Hiroshi Hozoji ,  Takashi Yokoyama ,  Noriyuki Kinjo ,  Aizo Kaneda ,  Junichi Saeki ,  Shozo Nakamura ,  Akio Hasebe ,  Hiroshi Kikuchi ,  Isamu Yoshida ,  Takashi Yamazaki ,  Kazuyoshi Oshima ,  Tetsuro Matsumoto

发明人： Gen Murakami ,  Kunihiro Tsubosaki ,  Masahiro Ichitani ,  Kunihiko Nishi ,  Ichiro Anjo ,  Asao Nishimura ,  Makoto Kitano ,  Akihiro Yaguchi ,  Sueo Kawai ,  Masatsugu Ogata ,  Syuuji Eguchi ,  Hiroyoshi Kokaku ,  Masanori Segawa ,  Hiroshi Hozoji ,  Takashi Yokoyama ,  Noriyuki Kinjo ,  Aizo Kaneda ,  Junichi Saeki ,  Shozo Nakamura ,  Akio Hasebe ,  Hiroshi Kikuchi ,  Isamu Yoshida ,  Takashi Yamazaki ,  Kazuyoshi Oshima ,  Tetsuro Matsumoto

IPC分类号： H01L2144

CPC分类号： H01L23/3107 ,  H01L23/4951 ,  H01L23/49555 ,  H01L23/49558 ,  H01L23/49568 ,  H01L23/49586 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/105 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/16245 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48799 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85205 ,  H01L2224/8592 ,  H01L2224/92147 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01092 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/144 ,  H05K1/181 ,  H05K3/3421 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/3512 ,  H01L2924/0695 ,  H01L2224/85399

摘要： As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

摘要翻译： 由于半导体芯片尺寸大，高集成度和加速度，所以难以将半导体芯片与包装中的引线组合在一起。 鉴于这种困难，已经采用称为半导体和引线堆叠和封装的称为“片上引线”或“引线芯片”结构的封装结构。 在该结构的封装中，根据本发明，内引线和半导体芯片的前端部之间的间隙比除引导端部和半导体芯片之外的内引线部分之间的间隙宽，从而减小 杂散容量，提高信号传输速率和减少电气噪声。