公开(公告)号：US5607866A

公开(公告)日：1997-03-04

申请号：US458112

申请日：1995-06-02

申请人： Kazushige Sato ,  Atsuo Watanabe ,  Kenichi Kikushima ,  Nobuo Owada ,  Masaya Iida

发明人： Kazushige Sato ,  Atsuo Watanabe ,  Kenichi Kikushima ,  Nobuo Owada ,  Masaya Iida

IPC分类号： H01L21/285 ,  H01L21/8249 ,  H01L27/06 ,  H01L21/265

CPC分类号： H01L21/8249 ,  H01L21/28518 ,  H01L27/0635 ,  Y10S148/009

摘要： In a method of fabricating a semiconductor device having a MISFET and/or bipolar transistor and/or a resistor formed with different surface portions of a single silicon semiconductor substrate in which a silicide layer is formed on each of source/drain regions of the MISFET and/or collector contact region and extrinsic base region of the bipolar transistor and/or contact regions of the resistor, the bipolar transistor has its emitter region formed by diffusing an impurity contained in doped polysilicon film serving as an emitter electrode of the bipolar transistor into a part of its base region. The resistor may have a resistive region formed in a surface portion of the substrate and may be covered with an insulating film and a doped polysilicon film thereon or may have a doped polysilicon film formed over a surface portion of the substrate as a resistor element. These doped polysilicon films in the resistor are films which are formed in the same step as that for the doped silicon film serving as the emitter electrode in the bipolar transistor. Each of the doped polysilicon film in the bipolar transistor and that in the resistor are covered with an insulating film before a refractory metal film is formed over a whole surface of the substrate to prevent formation of silicide films on the doped polysilicon films in the bipolar transistor and resistor.

摘要翻译： 在制造具有MISFET和/或双极晶体管和/或形成有单晶硅半导体衬底的不同表面部分的电阻器的半导体器件的方法中，其中在MISFET的每个源极/漏极区域上形成硅化物层， /或集电极接触区域和双极性晶体管的非本征基极区域和/或电阻器的接触区域，双极晶体管的发射极区域通过将掺杂多晶硅膜中所含的杂质扩散到双极型晶体管的发射电极而形成， 其基地区的一部分。 电阻器可以具有形成在衬底的表面部分中的电阻区域，并且可以在其上覆盖绝缘膜和掺杂多晶硅膜，或者可以在衬底的表面部分上形成作为电阻器元件的掺杂多晶硅膜。 电阻器中的这些掺杂多晶硅膜是与双极晶体管中的发射极电极的掺杂硅膜相同的步骤形成的膜。 在双极晶体管的整个表面上形成耐火金属膜之前，双极晶体管中的每个掺杂多晶硅膜和电阻器中的掺杂多晶硅膜都被绝缘膜覆盖，以防止在双极晶体管中的掺杂多晶硅膜上形成硅化物膜 和电阻。

公开(公告)号：US5506156A

公开(公告)日：1996-04-09

申请号：US279087

申请日：1994-07-22

申请人： Atsuo Watanabe ,  Kazushige Sato ,  Takahiro Nagano ,  Shoji Shukuri ,  Takashi Nishida

发明人： Atsuo Watanabe ,  Kazushige Sato ,  Takahiro Nagano ,  Shoji Shukuri ,  Takashi Nishida

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L21/265

CPC分类号： H01L21/8249 ,  Y10S148/009

摘要： A semiconductor device includes a plurality of semiconductor regions of a first conductive type and a plurality of semiconductor regions of a second conductive type. AMOS transistor having a channel of the second conductive type is formed in the semiconductor regions of the first conductive type, and a bipolar transistor and a MOS transistor having a channel of the first conductive type are formed in the semiconductor regions of the second conductive type. Each of the semiconductor regions of the first conductive type is made up of a semiconductor layer where the impurity concentration decreases with the depth from the surface thereof, a first buried layer of the first conductive type which is formed in a semiconductor substrate and where the impurity concentration distribution in the direction of thickness has a single peak value, and a second buried layer of the first conductive type which is formed between the semiconductor layer and the first buried layer and where the impurity concentration distribution in the direction of thickness has a single peak value. The first and second buried layers are formed by the ion implantation method, after an epitaxial growth process and a field oxidation process have been completed.

摘要翻译： 半导体器件包括多个第一导电类型的半导体区域和第二导电类型的多个半导体区域。 具有第二导电类型的沟道的AMOS晶体管形成在第一导电类型的半导体区域中，并且在第二导电类型的半导体区域中形成具有第一导电类型的沟道的双极晶体管和MOS晶体管。 第一导电类型的半导体区域由半导体层构成，其中杂质浓度随着其表面的深度而减小，第一导电类型的第一掩埋层形成在半导体衬底中，并且杂质 在厚度方向上的浓度分布具有单个峰值，并且形成在半导体层和第一掩埋层之间的第一导电类型的第二掩埋层，并且其中厚度方向上的杂质浓度分布具有单峰 值。 在外延生长处理和场氧化处理完成之后，通过离子注入法形成第一和第二掩埋层。

公开(公告)号：US5055904A

公开(公告)日：1991-10-08

申请号：US495762

申请日：1990-03-19

申请人： Masataka Minami ,  Kazushige Sato ,  Atsuo Watanabe ,  Shoji Shukuri ,  Takashi Nishida ,  Takahiro Nagano

发明人： Masataka Minami ,  Kazushige Sato ,  Atsuo Watanabe ,  Shoji Shukuri ,  Takashi Nishida ,  Takahiro Nagano

IPC分类号： H01L21/8249 ,  H01L27/06 ,  H01L27/11

CPC分类号： H01L27/0623 ,  H01L27/1112 ,  Y10S257/903

摘要： A semicondcutor device and a manufacturing method thereof are disclosed in which higher integration can be achieved without increasing the total manufacturing steps. The semiconductor device includes at least two MOS transistors having the same channel types, the gate electrodes of which are constructed of polycrystal silicon layers which contain an impurity, and a bipolar transistor, the base electrode of which is constructed of a polycrystal silicon layer which contains and impurity. In particular, the respective gate electrodes of the two MOS transistors contain impurities of different conductivity types from one another.

摘要翻译： 公开了一种半切割器件及其制造方法，其中可以在不增加总制造步骤的情况下实现更高的集成度。 半导体器件包括至少两个具有相同沟道类型的MOS晶体管，其栅电极由含有杂质的多晶硅层构成;以及双极晶体管，其基极由多晶硅层构成，该多晶硅层含有 和杂质。 特别地，两个MOS晶体管的各个栅电极彼此具有不同导电类型的杂质。

公开(公告)号：US5523598A

公开(公告)日：1996-06-04

申请号：US261133

申请日：1994-06-14

申请人： Atsuo Watanabe ,  Kazushige Sato

发明人： Atsuo Watanabe ,  Kazushige Sato

IPC分类号： H01L21/3205 ,  H01L21/8244 ,  H01L23/52 ,  H01L27/11 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/1104

摘要： The gate electrodes of the driver MISFETs, transfer MISFETs and load MISFETS of the static random access memory (SRAM) are formed of the first-level conductive layer deposited over the main surface of the semiconductor substrate. The gate electrodes, power source voltage line, reference voltage line, local interconnection lines, and complementary data lines, all making up the conductive layers of the SRAM memory cell, are formed of different conductive layers, i.e. conductive layers of different levels. The local interconnection lines and the reference voltage line or power source voltage line are arranged, with respect to a plan view of the main surface of the substrate, to cross each other and a capacitance is formed in the intersecting regions.

摘要翻译： 静电随机存取存储器（SRAM）的驱动器MISFET，转移MISFET和负载MISFETS的栅电极由沉积在半导体衬底的主表面上的第一级导电层形成。 所有构成SRAM存储单元的导电层的栅电极，电源电压线，参考电压线，局部互连线和互补数据线由不同导电层，即不同级别的导电层形成。 相对于基板的主表面的平面图，布置本地互连线和参考电压线或电源电压线，以便在交叉区域中形成电容。

公开(公告)号：US5371023A

公开(公告)日：1994-12-06

申请号：US895815

申请日：1992-06-09

申请人： Masataka Minami ,  Mitsuru Hiraki ,  Kazuo Yano ,  Atsuo Watanabe ,  Kouichi Seki ,  Takahiro Nagano ,  Kazushige Sato ,  Keiichi Yoshizumi ,  Ryuichi Izawa

发明人： Masataka Minami ,  Mitsuru Hiraki ,  Kazuo Yano ,  Atsuo Watanabe ,  Kouichi Seki ,  Takahiro Nagano ,  Kazushige Sato ,  Keiichi Yoshizumi ,  Ryuichi Izawa

IPC分类号： H01L27/06 ,  H01L27/105 ,  H01L21/20

CPC分类号： H01L27/105 ,  H01L27/0623

摘要： A novel gate circuit is disclosed. A first semiconductor switch includes a couple of main terminals connected between a first potential level and an output node, in which a high impedance state is held in response to an input signal having a first logic level and a second logic level, and the impedance state changes from high to low only during a transient period when the input signal changes substantially from the first to second logic level. A second semiconductor switch includes a couple of main terminals inserted between a second potential level different from the first potential level and the output node, in which a high impedance state is held in response to the input signal, and the impedance state changes from high to low only during a transient period when the input signal changes from the second to first logic level.

摘要翻译： 公开了一种新颖的门电路。 第一半导体开关包括连接在第一电位电平和输出节点之间的一对主端子，其中响应于具有第一逻辑电平和第二逻辑电平的输入信号而保持高阻抗状态，并且阻抗状态 仅在输入信号从第一逻辑电平变化到第二逻辑电平的过渡期间从高变化为低电平。 第二半导体开关包括插入在与第一电位电平不同的第二电位电平和输出节点之间的一对主端子，其中响应于输入信号保持高阻抗状态，并且阻抗状态从高变为 仅在输入信号从第二逻辑电平变为第一逻辑电平的瞬态期间为低电平。

公开(公告)号：US08134207B2

公开(公告)日：2012-03-13

申请号：US12028157

申请日：2008-02-08

申请人： Atsuo Watanabe

发明人： Atsuo Watanabe

IPC分类号： H01L29/66 ,  H01L27/12 ,  H01L29/786 ,  H01L21/02 ,  H01L21/70

CPC分类号： H01L27/1203 ,  H01L21/76283 ,  H01L21/76286 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41775 ,  H01L29/66325 ,  H01L29/66681 ,  H01L29/7394 ,  H01L29/7824

摘要： In a high breakdown voltage semiconductor element among elements integrated together on an SOI substrate in which its rated voltage is shared between an embedded oxide layer and a drain region formed by an element active layer, both high integration and high breakdown voltage are realized while also securing suitability for practical implementation and practical use. The high breakdown voltage is realized without hampering size reduction of the element by forming an electrically floating layer of a conductivity type opposite to that of the drain region at the surface of the drain region. Further, the thickness of the embedded oxide layer is reduced to a level suitable for the practical implementation and practical use by setting the thickness of the element active layer of the SOI substrate at 30 μm or more.

摘要翻译： 在集成在SOI衬底上的元件之间的高耐压电压半导体元件中，其中在由衬底的氧化物层和由元件有源层形成的漏极区域之间共享额定电压，实现高集成度和高​​击穿电压，同时还确保 适用于实际实施和实际应用。 通过在漏极区的表面形成与漏极区相反的导电类型的电浮置层，实现了高的击穿电压，而不会妨碍元件的尺寸减小。 此外，通过将SOI衬底的元件有源层的厚度设定为30μm以上，将嵌入氧化物层的厚度减小到适于实际实现和实际应用的水平。

公开(公告)号：US08081781B2

公开(公告)日：2011-12-20

申请号：US11814791

申请日：2006-02-23

申请人： Atsuo Watanabe

发明人： Atsuo Watanabe

IPC分类号： H02B1/00

CPC分类号： H04S5/02 ,  H03F3/181 ,  H03F3/217 ,  H03F3/68 ,  H03F2200/03

摘要： For achieving an audio reproduction with high sound quality, in a multi-channel A/V amplifier, front speakers are driven with a parallel-drive bi-amplifier arrangement upon stereo reproduction. In the case of the multi-channel reproduction mode, the switching circuit allows an output signal of each channel of the decoder to be sent to speakers via amplifiers for each channel in one-to-one correspondence. On the other hand, in the case of the 2-channel stereo reproduction mode, the switching circuit allows at least two amplifiers among the plurality of amplifiers to be connected in parallel between the output signal for each of the channels L and R of the decoder and the speakers for each of the channels L and R, and also allows the timing of the output signals of the respective amplifiers to be varied.

摘要翻译： 为了实现高音质的音频再现，在多声道A / V放大器中，在立体声再现时，前置扬声器由并行驱动双放大器布置驱动。 在多声道再现模式的情况下，切换电路允许解码器的每个声道的输出信号通过一个对应的每个声道的放大器发送到扬声器。 另一方面，在2声道立体声再现模式的情况下，切换电路允许多个放大器中的至少两个放大器并联连接在解码器的每个通道L和R的输出信号之间 以及每个通道L和R的扬声器，并且还允许各个放大器的输出信号的定时改变。

公开(公告)号：US20080153216A1

公开(公告)日：2008-06-26

申请号：US12071186

申请日：2008-02-19

申请人： Rajesh Kumar ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ohyanagi ,  Atsuo Watanabe

发明人： Rajesh Kumar ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ohyanagi ,  Atsuo Watanabe

IPC分类号： H01L21/82

CPC分类号： H01L29/1608 ,  H01L27/098 ,  H01L29/0619 ,  H01L29/66068 ,  H01L29/8083

摘要： A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion; forming a gate layer on an inner wall of each first trench by an epitaxial growth method; forming a first insulation film on the surface of the semiconductor substrate; forming a gate electrode on the first insulation film for connecting to the gate layer electrically; forming a source electrode on the first insulation film for connecting to the first semiconductor layer in the cell portion; and forming a drain electrode connected to the silicon carbide substrate electrically.

摘要翻译： 碳化硅半导体器件的制造方法包括以下步骤：制备包括碳化硅衬底，漂移层和第一半导体层的半导体衬底; 在单元部分中形成多个第一沟槽; 通过外延生长法在每个第一沟槽的内壁上形成栅极层; 在所述半导体衬底的表面上形成第一绝缘膜; 在所述第一绝缘膜上形成用于电连接到所述栅极层的栅电极; 在所述第一绝缘膜上形成用于连接到所述单元部分中的所述第一半导体层的源电极; 以及电连接到所述碳化硅衬底的漏电极。

公开(公告)号：US20070241338A1

公开(公告)日：2007-10-18

申请号：US11783611

申请日：2007-04-10

申请人： Tsuyoshi Yamamoto ,  Toshio Sakakibara ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ooyanagi ,  Atsuo Watanabe

发明人： Tsuyoshi Yamamoto ,  Toshio Sakakibara ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ooyanagi ,  Atsuo Watanabe

IPC分类号： H01L31/0312

CPC分类号： H01L29/1608 ,  H01L29/0843 ,  H01L29/1066 ,  H01L29/8083 ,  H01L29/872

摘要： A SiC semiconductor device includes: a SiC substrate having a drain layer, a drift layer and a source layer stacked in this order; multiple trenches penetrating the source layer and reaching the drift layer; a gate layer on a sidewall of each trench; an insulation film on the sidewall of each trench covering the gate layer; a source electrode on the source layer; and a diode portion in or under the trench contacting the drift layer to provide a diode. The drift layer between the gate layer on the sidewalls of adjacent two trenches provides a channel region. The diode portion is coupled with the source electrode, and insulated from the gate layer with the insulation film.

摘要翻译： SiC半导体器件包括：具有漏极层，漂移层和源极层的SiC衬底; 多个沟槽穿透源层并到达漂移层; 每个沟槽的侧壁上的栅极层; 覆盖所述栅极层的每个沟槽的侧壁上的绝缘膜; 源极上的源电极; 以及与沟槽接触的沟槽中或下方的二极管部分，以提供二极管。 相邻两个沟槽的侧壁上的栅极层之间的漂移层提供沟道区域。 二极管部分与源电极耦合，并与绝缘膜与栅极层绝缘。

公开(公告)号：US20070221924A1

公开(公告)日：2007-09-27

申请号：US11802810

申请日：2007-05-25

申请人： Takasumi Ohyanagi ,  Atsuo Watanabe ,  Rajesh Malhan ,  Tsuyoshi Yamamoto ,  Toshiyuki Morishita

发明人： Takasumi Ohyanagi ,  Atsuo Watanabe ,  Rajesh Malhan ,  Tsuyoshi Yamamoto ,  Toshiyuki Morishita

IPC分类号： H01L29/772

CPC分类号： H01L29/66416 ,  H01L29/1608 ,  H01L29/7722 ,  H01L29/8083

摘要： A silicon carbide semiconductor device such as JFET, SIT and the like is provided for accomplishing a reduction in on-resistance and high-speed switching operations. In the JFET or SIT which turns on/off a current with a depletion layer extending in a channel between a gate region formed along trench grooves, a gate contact layer and a gate electrode, which can be supplied with voltages from the outside, are formed on one surface of a semiconductor substrate or on the bottom of the trench groove. A metal conductor (virtual gate electrode) is formed in ohmic contact with a p++ contact layer of the gate region on the bottom of the trench grooves independently of the gate electrode. The virtual gate electrode is electrically isolated from the gate electrode and an external wire.

摘要翻译： 提供诸如JFET，SIT等的碳化硅半导体器件用于实现导通电阻和高速开关操作的降低。 在JFET或SIT中，形成在沿着沟槽形成的栅极区之间的沟道中延伸的耗尽层的电流，可以从外部供应电压的栅极接触层和栅极电极 在半导体衬底的一个表面上或在沟槽槽的底部。 金属导体（虚拟栅电极）与沟槽沟槽底部的栅极区域的p ++接触层独立于栅电极形成欧姆接触。 虚拟栅电极与栅极电极和外部电线电隔离。