公开(公告)号：US20060214200A1

公开(公告)日：2006-09-28

申请号：US11386850

申请日：2006-03-23

申请人： Ken-ichi Nonaka ,  Hideki Hashimoto ,  Seiichi Yokoyama ,  Kensuke Iwanaga ,  Yoshimitsu Saito

发明人： Ken-ichi Nonaka ,  Hideki Hashimoto ,  Seiichi Yokoyama ,  Kensuke Iwanaga ,  Yoshimitsu Saito

IPC分类号： H01L31/113

CPC分类号： H01L29/7722 ,  Y10S438/931

摘要： A junction semiconductor device having a drain region comprising a low-resistance layer of a first conductive type formed on one surface of a semiconductor crystal, a source region comprising a low-resistance layer of a first conductive type formed on the other surface of the semiconductor crystal, a gate region of a second conductive type formed on the periphery of the source region, a high-resistance layer of a first conductive type between the source region and the drain region, and a recombination-inhibiting semiconductor layer of a second conductive type provided in the vicinity of the surface of the semiconductor crystal between the gate region and the source region.

摘要翻译： 一种结半导体器件，具有包括形成在半导体晶体的一个表面上的第一导电类型的低电阻层的漏极区域，包括形成在半导体的另一个表面上的第一导电类型的低电阻层的源极区域 晶体，形成在源极区域周围的第二导电类型的栅极区域，在源极区域和漏极区域之间的第一导电类型的高电阻层，以及第二导电类型的复合抑制半导体层 设置在栅极区域和源极区域之间的半导体晶体的表面附近。

公开(公告)号：US07544552B2

公开(公告)日：2009-06-09

申请号：US11386661

申请日：2006-03-23

申请人： Ken-ichi Nonaka ,  Hideki Hashimoto ,  Seiichi Yokoyama ,  Kensuke Iwanaga ,  Yoshimitsu Saito ,  Hiroaki Iwakuro ,  Masaaki Shimizu ,  Yusuke Fukuda ,  Koichi Nishikawa ,  Yusuke Maeyama

发明人： Ken-ichi Nonaka ,  Hideki Hashimoto ,  Seiichi Yokoyama ,  Kensuke Iwanaga ,  Yoshimitsu Saito ,  Hiroaki Iwakuro ,  Masaaki Shimizu ,  Yusuke Fukuda ,  Koichi Nishikawa ,  Yusuke Maeyama

IPC分类号： H01L21/337 ,  H01L29/772 ,  H01L21/339 ,  H01L21/338 ,  H01L29/768 ,  H01L29/78

CPC分类号： H01L29/7722

摘要： A method for manufacturing a junction semiconductor device, having a step for forming a first high-resistance layer, a step for forming a channel-doped layer, a step for forming a second high-resistance layer, a step for forming a low-resistance layer of a first conductive type that acts as a source region, a step for performing partial etching to a midway depth of the second high-resistance layer and the low-resistance layer, a step for forming a gate region below the portion etched in the etching step, and a step for forming a protective film on the surface of the region between the gate region and the source region. A gate region is formed using relatively low energy ion implantation in the surface that has been etched in advance to a height that is between the lower surface of the source area and the upper surface of the channel-doped layer.

摘要翻译： 一种用于制造具有形成第一高电阻层的步骤的接合半导体器件的制造方法，形成沟道掺杂层的步骤，用于形成第二高电阻层的步骤，形成低电阻的步骤 作为源极区域的第一导电类型的层，用于对第二高电阻层和低电阻层的中间深度进行部分蚀刻的步骤，用于在第二高电阻层和低电阻层的蚀刻部分的下方形成栅极区域的步骤 蚀刻步骤，以及在栅极区域和源极区域之间的区域的表面上形成保护膜的步骤。 在表面中使用相对较低能量的离子注入，预先将蚀刻的源极区域的下表面和沟道掺杂层的上表面之间的高度形成为栅极区域。

公开(公告)号：US20060216879A1

公开(公告)日：2006-09-28

申请号：US11386661

申请日：2006-03-23

申请人： Ken-ichi Nonaka ,  Hideki Hashimoto ,  Seiichi Yokoyama ,  Kensuke Iwanaga ,  Yoshimitsu Saito ,  Hiroaki Iwakuro ,  Masaaki Shimizu ,  Yusuke Fukuda ,  Koichi Nishikawa ,  Yusuke Maeyama

发明人： Ken-ichi Nonaka ,  Hideki Hashimoto ,  Seiichi Yokoyama ,  Kensuke Iwanaga ,  Yoshimitsu Saito ,  Hiroaki Iwakuro ,  Masaaki Shimizu ,  Yusuke Fukuda ,  Koichi Nishikawa ,  Yusuke Maeyama

IPC分类号： H01L21/337

CPC分类号： H01L29/7722

摘要： A method for manufacturing a junction semiconductor device, having a step for forming a first high-resistance layer, a step for forming a channel-doped layer, a step for forming a second high-resistance layer, a step for forming a low-resistance layer of a first conductive type that acts as a source region, a step for performing partial etching to a midway depth of the second high-resistance layer and the low-resistance layer, a step for forming a gate region below the portion etched in the etching step, and a step for forming a protective film on the surface of the region between the gate region and the source region. A gate region is formed using relatively low energy ion implantation in the surface that has been etched in advance to a height that is between the lower surface of the source area and the upper surface of the channel-doped layer.

公开(公告)号：US07867836B2

公开(公告)日：2011-01-11

申请号：US12203660

申请日：2008-09-03

申请人： Ken-ichi Nonaka ,  Hideki Hashimoto ,  Seiichi Yokoyama ,  Kensuke Iwanaga ,  Yoshimitsu Saito

发明人： Ken-ichi Nonaka ,  Hideki Hashimoto ,  Seiichi Yokoyama ,  Kensuke Iwanaga ,  Yoshimitsu Saito

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/7722 ,  Y10S438/931

摘要： A method for manufacturing a junction semiconductor device having a drain region including a low-resistance layer of a first conductive type formed on one surface of a semiconductor crystal, a source region including a low-resistance layer of a first conductive type formed on the other surface of the semiconductor crystal, a gate region of a second conductive type formed on the periphery of the source region, a high-resistance layer of a first conductive type between the source region and the drain region, and a recombination-inhibiting semiconductor layer of a second conductive type provided in the vicinity of the surface of the semiconductor crystal between the gate region and the source region.

摘要翻译： 一种用于制造具有形成在半导体晶体的一个表面上的具有第一导电类型的低电阻层的漏极区域的结半导体器件的方法，包括形成在另一个上的第一导电类型的低电阻层的源极区域 半导体晶体的表面，形成在源极区域周围的第二导电类型的栅极区域，在源极区域和漏极区域之间的第一导电类型的高电阻层，以及复合抑制半导体层 设置在栅极区域和源极区域之间的半导体晶体的表面附近的第二导电类型。

公开(公告)号：US07449734B2

公开(公告)日：2008-11-11

申请号：US11386850

申请日：2006-03-23

申请人： Ken-ichi Nonaka ,  Hideki Hashimoto ,  Seiichi Yokoyama ,  Kensuke Iwanaga ,  Yoshimitsu Saito

发明人： Ken-ichi Nonaka ,  Hideki Hashimoto ,  Seiichi Yokoyama ,  Kensuke Iwanaga ,  Yoshimitsu Saito

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/119

CPC分类号： H01L29/7722 ,  Y10S438/931

摘要： A junction semiconductor device having a drain region including a low-resistance layer of a first conductive type formed on one surface of a semiconductor crystal, a source region including a low-resistance layer of a first conductive type formed on the other surface of the semiconductor crystal, a gate region of a second conductive type formed on the periphery of the source region, a high-resistance layer of a first conductive type between the source region and the drain region, and a recombination-inhibiting semiconductor layer of a second conductive type provided in the vicinity of the surface of the semiconductor crystal between the gate region and the source region.

摘要翻译： 具有形成在半导体晶体的一个表面上的具有第一导电类型的低电阻层的漏极区的结半导体器件，包括形成在半导体的另一个表面上的第一导电类型的低电阻层的源极区域 晶体，形成在源极区域周围的第二导电类型的栅极区域，在源极区域和漏极区域之间的第一导电类型的高电阻层，以及第二导电类型的复合抑制半导体层 设置在栅极区域和源极区域之间的半导体晶体的表面附近。

公开(公告)号：US20090004790A1

公开(公告)日：2009-01-01

申请号：US12203660

申请日：2008-09-03

申请人： Ken-ichi NONAKA ,  Hideki Hashimoto ,  Seiichi Yokoyama ,  Kensuke Iwanaga ,  Yoshimitsu Saito

发明人： Ken-ichi NONAKA ,  Hideki Hashimoto ,  Seiichi Yokoyama ,  Kensuke Iwanaga ,  Yoshimitsu Saito

IPC分类号： H01L21/337

CPC分类号： H01L29/7722 ,  Y10S438/931

摘要： A method for manufacturing a junction semiconductor device having a drain region including a low-resistance layer of a first conductive type formed on one surface of a semiconductor crystal, a source region including a low-resistance layer of a first conductive type formed on the other surface of the semiconductor crystal, a gate region of a second conductive type formed on the periphery of the source region, a high-resistance layer of a first conductive type between the source region and the drain region, and a recombination-inhibiting semiconductor layer of a second conductive type provided in the vicinity of the surface of the semiconductor crystal between the gate region and the source region.

摘要翻译： 一种用于制造具有形成在半导体晶体的一个表面上的具有第一导电类型的低电阻层的漏极区域的结半导体器件的方法，包括形成在另一个上的第一导电类型的低电阻层的源极区域 半导体晶体的表面，形成在源极区域周围的第二导电类型的栅极区域，在源极区域和漏极区域之间的第一导电类型的高电阻层，以及复合抑制半导体层 设置在栅极区域和源极区域之间的半导体晶体的表面附近的第二导电类型。

公开(公告)号：US07709862B2

公开(公告)日：2010-05-04

申请号：US11496627

申请日：2006-08-01

申请人： Ken-ichi Nonaka ,  Hideki Hashimoto ,  Seiichi Yokoyama ,  Hiroaki Iwakuro ,  Koichi Nishikawa ,  Masaaki Shimizu ,  Yusuke Fukuda

发明人： Ken-ichi Nonaka ,  Hideki Hashimoto ,  Seiichi Yokoyama ,  Hiroaki Iwakuro ,  Koichi Nishikawa ,  Masaaki Shimizu ,  Yusuke Fukuda

IPC分类号： H01L29/76

CPC分类号： H01L29/8083 ,  H01L21/0465 ,  H01L21/266 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/66068 ,  Y10S438/931

摘要： A method for manufacturing an ion implantation mask is disclosed which includes the steps of: forming an oxide film as a protective film over the entire surface of a semiconductor substrate; forming a thin metal film over the oxide film; and forming an ion-inhibiting layer composed of an ion-inhibiting metal over the thin metal film. The obtained ion implantation mask is used to form a deeper selectively electroconductive region.

摘要翻译： 公开了一种用于制造离子注入掩模的方法，其包括以下步骤：在半导体衬底的整个表面上形成氧化膜作为保护膜; 在氧化膜上形成薄金属膜; 以及在所述薄金属膜上形成由离子抑制金属构成的离子抑制层。 所获得的离子注入掩模用于形成更深的选择性导电区域。

公开(公告)号：US08105927B2

公开(公告)日：2012-01-31

申请号：US12716916

申请日：2010-03-03

申请人： Ken-ichi Nonaka ,  Hideki Hashimoto ,  Seiichi Yokoyama ,  Hiroaki Iwakuro ,  Koichi Nishikawa ,  Masaaki Shimizu ,  Yusuke Fukuda

发明人： Ken-ichi Nonaka ,  Hideki Hashimoto ,  Seiichi Yokoyama ,  Hiroaki Iwakuro ,  Koichi Nishikawa ,  Masaaki Shimizu ,  Yusuke Fukuda

IPC分类号： H01L21/425

CPC分类号： H01L29/8083 ,  H01L21/0465 ,  H01L21/266 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/66068 ,  Y10S438/931

摘要： A method for manufacturing an ion implantation mask is disclosed which includes the steps of: forming an oxide film as a protective film over the entire surface of a semiconductor substrate; forming a thin metal film over the oxide film; and forming an ion-inhibiting layer composed of an ion-inhibiting metal over the thin metal film. The obtained ion implantation mask is used to form a deeper selectively electroconductive region.

摘要翻译： 公开了一种用于制造离子注入掩模的方法，其包括以下步骤：在半导体衬底的整个表面上形成氧化膜作为保护膜; 在氧化膜上形成薄金属膜; 以及在所述薄金属膜上形成由离子抑制金属构成的离子抑制层。 所获得的离子注入掩模用于形成更深的选择性导电区域。

公开(公告)号：US20070032002A1

公开(公告)日：2007-02-08

申请号：US11496627

申请日：2006-08-01

申请人： Ken-ichi Nonaka ,  Hideki Hashimoto ,  Seiichi Yokoyama ,  Hiroaki Iwakuro ,  Koichi Nishikawa ,  Masaaki Shimizu ,  Yusuke Fukuda

发明人： Ken-ichi Nonaka ,  Hideki Hashimoto ,  Seiichi Yokoyama ,  Hiroaki Iwakuro ,  Koichi Nishikawa ,  Masaaki Shimizu ,  Yusuke Fukuda

IPC分类号： H01L21/337 ,  H01L21/425 ,  H01L21/265 ,  H01L21/336 ,  H01L21/00

CPC分类号： H01L29/8083 ,  H01L21/0465 ,  H01L21/266 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/66068 ,  Y10S438/931

摘要： A method for manufacturing an ion implantation mask is disclosed which includes the steps of: forming an oxide film as a protective film over the entire surface of a semiconductor substrate; forming a thin metal film over the oxide film; and forming an ion-inhibiting layer composed of an ion-inhibiting metal over the thin metal film. The obtained ion implantation mask is used to form a deeper selectively electroconductive region.

摘要翻译： 公开了一种用于制造离子注入掩模的方法，其包括以下步骤：在半导体衬底的整个表面上形成氧化膜作为保护膜; 在氧化膜上形成薄金属膜; 以及在所述薄金属膜上形成由离子抑制金属构成的离子抑制层。 所获得的离子注入掩模用于形成更深的选择性导电区域。

公开(公告)号：US20110169015A1

公开(公告)日：2011-07-14

申请号：US13060697

申请日：2009-08-25

申请人： Yuki Negoro ,  Akihiko Horiuchi ,  Kensuke Iwanaga ,  Seiichi Yokoyama ,  Hideki Hashimoto ,  Kenichi Nonaka ,  Yusuke Maeyama ,  Masashi Sato ,  Masaaki Shimizu

发明人： Yuki Negoro ,  Akihiko Horiuchi ,  Kensuke Iwanaga ,  Seiichi Yokoyama ,  Hideki Hashimoto ,  Kenichi Nonaka ,  Yusuke Maeyama ,  Masashi Sato ,  Masaaki Shimizu

IPC分类号： H01L29/161 ,  H01L21/56

CPC分类号： H01L29/732 ,  H01L23/3171 ,  H01L23/3192 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/42304 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/6609 ,  H01L29/66295 ,  H01L29/66416 ,  H01L29/7722 ,  H01L29/8613 ,  H01L2224/06181 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00

摘要： Disclosed is a bipolar semiconductor device which is capable of reducing the surface state density of a bipolar transistor and increasing the current gain of the transistor, thereby improving the transistor performance. A bipolar semiconductor device (100) has a surface protective film (30) on the surface of a semiconductor element. The surface protective film is composed of a thermal oxide film (31) formed on the surface of the semiconductor element, and a deposited oxide film (32) formed on the thermal oxide film. The deposited oxide film contains at least one of hydrogen element and nitrogen element in an amount of not less than 1018 cm−3.

摘要翻译： 公开了能够降低双极晶体管的表面状态密度并增加晶体管的电流增益的双极半导体器件，从而提高晶体管的性能。 双极半导体器件（100）在半导体元件的表面上具有表面保护膜（30）。 表面保护膜由形成在半导体元件的表面上的热氧化膜（31）和形成在热氧化膜上的沉积氧化物膜（32）构成。 沉积的氧化物膜含有不少于1018cm-3的氢元素和氮元素中的至少一种。