利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

8 条记录 (耗时 0.018 秒)

    Reconfigurable memory
    5.
    发明授权
    Reconfigurable memory 失效
    可重构内存

    公开(公告)号：US5134584A

    公开(公告)日：1992-07-28

    申请号：US223084

    申请日：1988-07-22

    申请人： Clifford H. Boler ,  Jeffrey A. Lukanc

    发明人： Clifford H. Boler ,  Jeffrey A. Lukanc

    IPC分类号： G11C29/00

    CPC分类号： G11C29/848 ,  G11C29/88

    摘要： A configurable device uses a plurality of parallel units which are made up of cells for storing individual bits of information. These cells are identified by address signals and selected to be interrogated. The selected cells are interrogated to determine information stored therein and a signal is produced which corresponds to that information. If a nonfunctional cell is detected within a parallel unit, that parallel unit may be decoupled from the interrogator. The remainder of the parallel units are shifted to different interrogators thereby effectively eliminating use of the decoupled parallel unit which contains the nonfunctional cell.

    摘要翻译： 可配置的设备使用由小区组成的多个并行单元，用于存储信息的各个位。 这些单元由地址信号识别并选择进行询问。 所选择的单元被询问以确定存储在其中的信息，并产生对应于该信息的信号。 如果在并行单元内检测到非功能单元，则该并联单元可能与询问器分离。 剩余的并行单元被移动到不同的询问器，从而有效地消除了包含非功能单元的解耦并联单元的使用。

    CMOS output buffer providing high drive current with minimum output signal distortion
    6.
    发明授权
    CMOS output buffer providing high drive current with minimum output signal distortion 失效
    CMOS输出缓冲器提供高驱动电流，最小输出信号失真

    公开(公告)号：US4638187A

    公开(公告)日：1987-01-20

    申请号：US782639

    申请日：1985-10-01

    申请人： Clifford H. Boler ,  William W. Leake ,  Surinder S. Rai ,  Gene B. Zemske

    发明人： Clifford H. Boler ,  William W. Leake ,  Surinder S. Rai ,  Gene B. Zemske

    IPC分类号： H03K19/00 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/0948 ,  H03K21/10

    CPC分类号： H03K19/01721 ,  H03K19/0013 ,  H03K19/00361 ,  H03K19/018521 ,  H03K19/09429 ,  H03K19/0948

    摘要： A CMOS output buffer provides high drive current without sacrificing speed and with minimum output signal distortion due to internal chip ground bounce or output signal ringing. The output buffer includes a pull-up circuit and a pull-down circuit which distribute switching current spikes over time. The pull-up circuit includes a P-channel FET and an N-channel FET connected in parallel between an output terminal and supply terminal V.sub.DD, with an inverter connected between the gates of the N-channel and P-channel FETs to provide the proper phase for the P-channel FET as well as delaying turn-on of the P-channel FET with respect to turn-on of the N-channel FET. The pull-down circuit includes a pair of N-channel FETs connected in parallel between the output terminal and ground, and a delay resistance connected between their gates so that turn-on of one of the N-channel FETs is delayed with respect to the other.

    摘要翻译： CMOS输出缓冲器提供高驱动电流，而不会牺牲速度，并且由于内部芯片地面反弹或输出信号振铃，输出信号失真最小。 输出缓冲器包括上拉电路和下拉电路，其随时间分配开关电流尖峰。 上拉电路包括在输出端子和电源端子VDD之间并联连接的P沟道FET和N沟道FET，反相器连接在N沟道和P沟道FET的栅极之间，以提供适当的 P沟道FET的相位以及相对于N沟道FET的导通来延迟P沟道FET的导通。 下拉电路包括在输出端和地之间并联连接的一对N沟道FET，以及连接在其栅极之间的延迟电阻，使得N沟道FET之一的导通相对于 其他。

    Reducing bipolar parasitic effects in IGFET devices
    7.
    发明授权
    Reducing bipolar parasitic effects in IGFET devices 失效
    减少IGFET器件中的双极寄生效应

    公开(公告)号：US4797724A

    公开(公告)日：1989-01-10

    申请号：US393891

    申请日：1982-06-30

    申请人： Clifford H. Boler ,  Marc D. Hartranft ,  Thomas E. Hendrickson

    发明人： Clifford H. Boler ,  Marc D. Hartranft ,  Thomas E. Hendrickson

    IPC分类号： H01L21/74 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/32 ,  H01L29/34 ,  H01L27/04 ,  H01L29/78

    CPC分类号： H01L29/0847 ,  H01L21/743 ,  H01L27/0921 ,  H01L29/1083 ,  H01L29/32 ,  H01L29/34

    摘要： An IGFET is presented which includes a relatively low resistance path across the source-substrate junction to prevent parasitic bipolar effects while maintaining high component density in integrated circuits. The low resistance path across the source-substrate junction is formed by various methods including damaging the crystal structure at the junction interface, supplementing the damaged junction with a heavily doped region underlying the source region and spiking metallurgy. A particular application of the invention allows the prevention of latchup in CMOS devices. The invention also allows the source region of an IGFET to serve the dual functions of a source for a MOSFET as well as an ohmic contact to the underlying well or substrate.

    摘要翻译： 提出了一种IGFET，其包括穿过源 - 衬底结的相对低的电阻路径，以防止寄生双极效应，同时在集成电路中保持高的组件密度。 通过各种方法形成源 - 衬底结的低电阻路径，包括损坏接合界面处的晶体结构，补偿受损结与源区下面的重掺杂区域和掺杂冶金。 本发明的特定应用允许防止CMOS器件中的闭锁。 本发明还允许IGFET的源极区域用于MOSFET的源极的双重功能以及与下面的阱或衬底的欧姆接触。