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    Etch pattern definition using a CVD organic layer as an anti-reflection coating and hardmask
    5.
    发明申请
    Etch pattern definition using a CVD organic layer as an anti-reflection coating and hardmask 审中-公开
    使用CVD有机层作为防反射涂层和硬掩模的蚀刻图案定义

    公开(公告)号：US20080197109A1

    公开(公告)日：2008-08-21

    申请号：US11981930

    申请日：2007-10-31

    申请人： David S. Mui ,  Wei Liu ,  Thorsten Lill ,  Christopher Dennis Bencher ,  Yuxiang May Wang

    发明人： David S. Mui ,  Wei Liu ,  Thorsten Lill ,  Christopher Dennis Bencher ,  Yuxiang May Wang

    IPC分类号： C23F1/00

    CPC分类号： H01L21/0276 ,  H01L21/28035 ,  H01L21/3081 ,  H01L21/3088 ,  H01L21/31138 ,  H01L21/3146 ,  H01L21/32137 ,  H01L21/32139

    摘要： A multilayer antireflective hard mask structure is disclosed. The structure comprises: (a) a CVD organic layer, wherein the CVD organic layer comprises carbon and hydrogen; and (b) a dielectric layer over the CVD organic layer. The dielectric layer is preferably a silicon oxynitride layer, while the CVD organic layer preferably comprises 70-80% carbon, 10-20% hydrogen and 5-15% nitrogen. Also disclosed are methods of forming and trimming such a multilayer antireflective hard mask structure. Further disclosed are methods of etching a substrate structure using a mask structure that contains a CVD organic layer and optionally has a dielectric layer over the CVD organic layer.

    摘要翻译： 公开了一种多层抗反射硬掩模结构。 该结构包括：（a）CVD有机层，其中CVD有机层包含碳和氢; 和（b）CVD有机层上的电介质层。 电介质层优选为氮氧化硅层，而CVD有机层优选包含70-80％的碳，10-20％的氢和5-15％的氮。 还公开了形成和修整这种多层抗反射硬掩模结构的方法。 还公开了使用包含CVD有机层并且可选地在CVD有机层上具有介电层的掩模结构来蚀刻衬底结构的方法。

    Ashable layers for reducing critical dimensions of integrated circuit features
    10.
    发明授权
    Ashable layers for reducing critical dimensions of integrated circuit features 失效
    用于降低集成电路特性的关键尺寸的可铺层

    公开(公告)号：US07105442B2

    公开(公告)日：2006-09-12

    申请号：US10154532

    申请日：2002-05-22

    申请人： Hongching Shan ,  Kenny L. Doan ,  Jingbao Liu ,  Michael S. Barnes ,  Hong D. Nguyen ,  Christopher Dennis Bencher ,  Christopher S. Ngai ,  Wendy H. Yeh ,  Eda Tuncel ,  Claes H. Bjorkman

    发明人： Hongching Shan ,  Kenny L. Doan ,  Jingbao Liu ,  Michael S. Barnes ,  Hong D. Nguyen ,  Christopher Dennis Bencher ,  Christopher S. Ngai ,  Wendy H. Yeh ,  Eda Tuncel ,  Claes H. Bjorkman

    IPC分类号： H01L21/44 ,  H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/31144 ,  G03F7/40 ,  H01L21/02115 ,  H01L21/02118 ,  H01L21/0271 ,  H01L21/31116 ,  H01L21/312 ,  H01L21/3146

    摘要： A method is described for decreasing the critical dimensions of integrated circuit features in which a first masking layer (101) is deposited, patterned and opened in the manner of typical feature etching, and a second masking layer (201) is deposited thereon prior to etching the underlying insulator. The second masking layer is advantageously coated in a substantially conformal manner. Opening the second masking layer while leaving material of the second layer on the sidewalls of the first masking layer as spacers leads to reduction of the feature critical dimension in the underlying insulator. Ashable masking materials, including amorphous carbon and organic materials are removable without CMP, thereby reducing costs. Favorable results are also obtained utilizing more than one masking layer (101, 301) underlying the topmost masking layer (302) from which the spacers are formed. Embodiments are also described in which slope etching replaces the addition of a separate spacer layer. Substructures formed in the fabrication process are also described. Spacers are also shown to be favorably employed in making feature-in-feature structures.

    摘要翻译： 描述了一种降低集成电路特征的关键尺寸的方法，其中以典型特征蚀刻的方式沉积，图案化和打开第一掩模层（101），并且在蚀刻之前沉积第二掩模层（201） 底层绝缘子。 有利地以基本上共形的方式涂覆第二掩模层。 打开第二掩蔽层，同时将第二层的材料留在第一掩模层的侧壁上作为间隔物导致下层绝缘体中的特征临界尺寸的减小。 包括无定形碳和有机材料在内的可湿性掩蔽材料可以不经CMP去除，从而降低成本。 利用形成间隔物的最上面的掩模层（302）下方的多于一个掩模层（101,301）也可获得有利的结果。 还描述了其中斜率蚀刻替代单独的间隔层的添加的实施例。 还描述了在制造过程中形成的子结构。 垫片也被用于制造特征特征结构。