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36 条记录 (耗时 0.038 秒)

    Semiconductor device having reduced oxidation interface
    3.
    发明授权
    Semiconductor device having reduced oxidation interface 有权
    半导体器件具有减少的氧化界面

    公开(公告)号：US06700202B2

    公开(公告)日：2004-03-02

    申请号：US10013182

    申请日：2001-12-07

    申请人： Judy H. Huang ,  Christopher Dennis Bencher ,  Sudha Rathi ,  Christopher S. Ngai ,  Bok Hoen Kim

    发明人： Judy H. Huang ,  Christopher Dennis Bencher ,  Sudha Rathi ,  Christopher S. Ngai ,  Bok Hoen Kim

    IPC分类号： H01L2348

    CPC分类号： H01L21/76834 ,  B08B7/0035 ,  C23C16/0245 ,  C23G5/00 ,  H01L21/02063 ,  H01L21/02068 ,  H01L21/02071 ,  H01L21/02074 ,  H01L21/31116 ,  H01L21/3148 ,  H01L21/3185 ,  H01L21/32136 ,  H01L21/76807 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A method and apparatus for reducing oxidation of an interface of a semiconductor device thereby improving adhesion of subsequently formed layers and/or devices is disclosed. The semiconductor device has at least a first layer and a second layer wherein the interface is disposed between said first and second layers. The method includes the steps of providing the first layer having a partially oxidized interface; introducing a hydrogen-containing plasma to the interface; reducing the oxidized interface and introducing second-layer-forming compounds to the hydrogen-containing plasma. A concomitant apparatus (i.e., a semiconductor device interface) has a first insulating layer, one or more conductive devices disposed within the insulating layer, the insulating layer and conductive devices defining the interface, wherein the interface is treated with a continuous plasma treatment to remove oxidation and deposit a second layer thereupon. The insulating layer of the interface is selected from oxides and nitrides and is preferably a nitride.

    摘要翻译： 公开了一种用于减少半导体器件的界面的氧化从而改善随后形成的层和/或器件的粘合性的方法和装置。 半导体器件具有至少第一层和第二层，其中界面设置在所述第一层和第二层之间。 该方法包括提供具有部分氧化界面的第一层的步骤; 向界面引入含氢等离子体; 还原氧化界面并将第二层形成化合物引入到含氢等离子体中。 伴随的装置（即，半导体器件接口）具有第一绝缘层，设置在绝缘层内的一个或多个导电器件，绝缘层和限定界面的导电器件，其中界面用连续等离子体处理来去除 氧化并沉积第二层。 界面的绝缘层选自氧化物和氮化物，优选为氮化物。

    H2-based plasma treatment to eliminate within-batch and batch-to-batch etch drift
    7.
    发明授权
    H2-based plasma treatment to eliminate within-batch and batch-to-batch etch drift 有权
    基于H2的等离子体处理，以消除批次间和批次间蚀刻漂移

    公开(公告)号：US07727906B1

    公开(公告)日：2010-06-01

    申请号：US11493679

    申请日：2006-07-26

    申请人： Sunil Shanker ,  Chi-I Lang ,  Minh Anh Nguyen ,  Judy H. Huang

    发明人： Sunil Shanker ,  Chi-I Lang ,  Minh Anh Nguyen ,  Judy H. Huang

    IPC分类号： H01L21/31

    CPC分类号： C23C16/045 ,  C23C16/4404 ,  C23C16/4405 ,  H01J37/32165 ,  H01L21/31604

    摘要： This invention relates to electronic device fabrication for making devices such as semiconductor wafers and resolves the detrimental fluorine loading effect on deposition in the reaction chamber of a HDP CVD apparatus used for forming dielectric layers in high aspect ratio, narrow width recessed features with a repeating dep/etch/dep process. The detrimental fluorine loading effect in the chamber on deposition uniformity is reduced and wafers are provided having less deposition thickness variations by employing the method using a passivation treatment and precoating of the chamber before substrates are processed. In a preferred process, after each wafer of a batch is finished, the passivation steps are repeated. In a further preferred process, after all the wafers of a batch are finished, the passivation and precoat procedure is repeated. A preferred passivation gas is a mixture of hydrogen and oxygen.

    摘要翻译： 本发明涉及用于制造诸如半导体晶片的器件的电子器件制造，并且解决了用于形成具有高纵横比，窄宽度凹陷特征的电介质层的HDP CVD设备的反应室中沉积的有害氟负载效应，具有重复的dep / etch / dep进程。 通过采用钝化处理的方法和在处理基板之前对涂层进行涂布，在沉积均匀性方面降低了室中对有害的氟负载效应并提供具有较小沉积厚度变化的晶片。 在优选的方法中，在批次的每个晶片完成之后，重复钝化步骤。 在另一优选方法中，在批料的所有晶片完成之后，重复钝化和预涂步骤。 优选的钝化气体是氢和氧的混合物。

    CVD flowable gap fill
    8.
    发明授权
    CVD flowable gap fill 有权

    公开(公告)号：US08580697B1

    公开(公告)日：2013-11-12

    申请号：US13031077

    申请日：2011-02-18

    申请人： Chi-I Lang ,  Judy H. Huang ,  Michael Barnes ,  Sunil Shanker

    发明人： Chi-I Lang ,  Judy H. Huang ,  Michael Barnes ,  Sunil Shanker

    IPC分类号： H01L21/02

    CPC分类号： H01L21/76837 ,  H01L21/02164 ,  H01L21/02216 ,  H01L21/02271 ,  H01L21/0234 ,  H01L21/31612 ,  H01L21/76826

    摘要： The present invention meets these needs by providing improved methods of filling gaps. In certain embodiments, the methods involve placing a substrate into a reaction chamber and introducing a vapor phase silicon-containing compound and oxidant into the chamber. Reactor conditions are controlled so that the silicon-containing compound and the oxidant are made to react and condense onto the substrate. The chemical reaction causes the formation of a flowable film, in some instances containing Si—OH, Si—H and Si—O bonds. The flowable film fills gaps on the substrates. The flowable film is then converted into a silicon oxide film, for example by plasma or thermal annealing. The methods of this invention may be used to fill high aspect ratio gaps, including gaps having aspect ratios ranging from 3:1 to 10:1.

    In situ deposition of a low K dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application
    9.
    发明授权
    In situ deposition of a low K dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application 失效
    原位沉积低K电介质层，阻挡层，蚀刻停止和抗反射涂层，用于大马士革应用

    公开(公告)号：US07470611B2

    公开(公告)日：2008-12-30

    申请号：US11301063

    申请日：2005-12-12

    申请人： Judy H. Huang

    发明人： Judy H. Huang

    IPC分类号： H01L21/314

    CPC分类号： H01L21/76829 ,  C23C16/325 ,  C30B25/105 ,  C30B29/36 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/0276 ,  H01L21/0445 ,  H01L21/314 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76834 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S438/931 ,  Y10S438/932 ,  Y10S438/952 ,  H01L2924/00

    摘要： The present invention provides a SiC material, formed according to certain process regimes, useful as a barrier layer, etch stop, and/or an ARC, in multiple levels, including the pre-metal dielectric (PMD) level, in IC applications and provides a dielectric layer deposited in situ with the SiC material for the barrier layers, and etch stops, and ARCs. The dielectric layer can be deposited with different precursors as the SiC material, but preferably with the same or similar precursors as the SiC material. The present invention is particularly useful for ICs using high diffusion copper as a conductive material. The invention may also utilize a plasma containing a reducing agent, such as ammonia, to reduce any oxides that may occur, particularly on metal surfaces such as copper filled features. The invention also provides processing regimes that include using an organosilane as a silicon and carbon source, perhaps independently of any other carbon source or hydrogen source, and preferably in the absence of a substantial amount of oxygen to produce a SiC with a dielectric constant of less than 7.0. This particular SiC material is useful in complex structures, such as a damascene structure and is conducive to in situ deposition, especially when used in multiple capacities for the different layers, such as the barrier layer, the etch stop, and the ARC and can include in situ deposition of the associated dielectric layer(s).

    摘要翻译： 本发明提供了在IC应用中，根据某些工艺方案形成的SiC材料，其可用作包括前金属电介质（PMD）水平在内的多层次的阻挡层，蚀刻停止层和/或ARC，并且提供 原位沉积有用于阻挡层的SiC材料的介电层，以及蚀刻停止层和ARC。 介电层可以作为SiC材料沉积不同的前体，但优选与SiC材料相同或相似的前体沉积。 本发明对于使用高扩散铜作为导电材料的IC特别有用。 本发明还可以利用含有诸如氨的还原剂的等离子体来减少可能发生的任何氧化物，特别是在诸如铜填充特征的金属表面上。 本发明还提供了处理方案，其包括使用有机硅烷作为硅和碳源，可能独立于任何其它碳源或氢源，并且优选在不存在大量氧的情况下产生介电常数较小的SiC 超过7.0。 这种特殊的SiC材料可用于复杂的结构，例如镶嵌结构，并且有利于原位沉积，特别是当用于不同层的多个容量时，例如阻挡层，蚀刻停止层和ARC，并且可以包括 相关电介质层的原位沉积。