公开(公告)号：US20130134372A1

公开(公告)日：2013-05-30

申请号：US13689026

申请日：2012-11-29

申请人： Kiwamu SAKUMA ,  Haruka KUSAI ,  Shosuke FUJII ,  Li ZHANG ,  Masahiro KIYOTOSHI ,  Masao SHINGU

发明人： Kiwamu SAKUMA ,  Haruka KUSAI ,  Shosuke FUJII ,  Li ZHANG ,  Masahiro KIYOTOSHI ,  Masao SHINGU

IPC分类号： H01L45/00 ,  H01L21/265

CPC分类号： H01L27/1157 ,  H01L21/265 ,  H01L21/845 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/1211 ,  H01L27/2436 ,  H01L27/2481 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/792 ,  H01L45/04

摘要： According to one embodiment, a semiconductor device includes first to n-th semiconductor layers (n is a natural number equal to or more than 2) being stacked in order from a surface of an insulating layer in a first direction perpendicular to the surface of the insulating layer, the first to n-th semiconductor layers extending in a second direction parallel to the surface of the insulating layer, the first to n-th semiconductor layers being insulated from each other, a common electrode connected to the first to n-th semiconductor layers in a first end of the second direction thereof, and a layer select transistor which uses the first to n-th semiconductor layers as channels and which selects one of the first to n-th semiconductor layers.

摘要翻译： 根据一个实施例，半导体器件包括第一至第n半导体层（n为等于或大于2的自然数），从绝缘层的表面依次堆叠在与第 绝缘层，所述第一至第n半导体层在与所述绝缘层的表面平行的第二方向上延伸，所述第一至第n半导体层彼此绝缘，公共电极连接到所述第一至第n 半导体层，其第二方向的第一端，以及使用第一至第n半导体层作为沟道并选择第一至第n半导体层之一的层选择晶体管。

公开(公告)号：US20130181184A1

公开(公告)日：2013-07-18

申请号：US13547567

申请日：2012-07-12

申请人： Kiwamu SAKUMA ,  Masahiro KIYOTOSHI ,  Atsuhiro KINOSHITA ,  Haruka KUSAI

发明人： Kiwamu SAKUMA ,  Masahiro KIYOTOSHI ,  Atsuhiro KINOSHITA ,  Haruka KUSAI

IPC分类号： H01L27/24 ,  H01L21/8234

CPC分类号： H01L45/1233 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/1211 ,  H01L27/222 ,  H01L27/2454 ,  H01L27/2481 ,  H01L29/7881 ,  H01L29/792 ,  H01L45/1206 ,  H01L45/1253

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes fin-type stacked layer structures. Each of the structures includes semiconductor layers stacked in a perpendicular direction. Assist gate electrodes are disposed in an in-plane direction and divided on a surface in the perpendicular direction of the structures.

公开(公告)号：US20120273747A1

公开(公告)日：2012-11-01

申请号：US13458042

申请日：2012-04-27

申请人： Masumi SAITOH ,  Toshinori NUMATA ,  Kiwamu SAKUMA ,  Haruka KUSAI ,  Takayuki ISHIKAWA

发明人： Masumi SAITOH ,  Toshinori NUMATA ,  Kiwamu SAKUMA ,  Haruka KUSAI ,  Takayuki ISHIKAWA

IPC分类号： H01L27/26 ,  H01L21/8239 ,  H01L27/088

CPC分类号： H01L21/823431 ,  H01L27/101 ,  H01L27/1211 ,  H01L27/2409 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a semiconductor device includes a fin type stacked layer structure which has first to third semiconductor layers, and first to third layer select transistors to select one of the first to third semiconductor layers. The second layer select transistor is normally on in the second semiconductor layer, and is controlled to be on or off in the first and third semiconductor layers. A channel region of the second semiconductor layer which is covered with a gate electrode of the second layer select transistor has a metal silicide.

摘要翻译： 根据一个实施例，半导体器件包括具有第一至第三半导体层的鳍式堆叠层结构以及选择第一至第三半导体层之一的第一至第三层选择晶体管。 第二层选择晶体管通常在第二半导体层中导通，并且在第一和第三半导体层中被控制为导通或截止。 被第二层选择晶体管的栅电极覆盖的第二半导体层的沟道区域具有金属硅化物。

公开(公告)号：US20120139030A1

公开(公告)日：2012-06-07

申请号：US13316603

申请日：2011-12-12

申请人： Kiwamu SAKUMA ,  Atsuhiro Kinoshita ,  Masahiro Kiyotoshi ,  Daisuke Hagishima ,  Koichi Muraoka

发明人： Kiwamu SAKUMA ,  Atsuhiro Kinoshita ,  Masahiro Kiyotoshi ,  Daisuke Hagishima ,  Koichi Muraoka

IPC分类号： H01L27/105 ,  H01L21/8239

CPC分类号： H01L29/42328 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： According to one embodiment, a nonvolatile semiconductor memory includes first to n-th (n is a natural number not less than 2) semiconductor layers in a first direction and extend in a second direction, and the semiconductor layers having a stair case pattern in a first end of the second direction, a common semiconductor layer connected to the first to n-th semiconductor layers commonly in the first end of the second direction, first to n-th layer select transistors which are provided in order from the first electrode side between the first electrode and the first to n-th memory strings, and first to n-th impurity regions which make the i-th layer select transistor (i is one of 1 to n) a normally-on state in the first end of the second direction of the i-th semiconductor layer.

摘要翻译： 根据一个实施例，非易失性半导体存储器包括在第一方向上的第一至第n（n是不小于2的自然数）半导体层，并且在第二方向上延伸，并且半导体层具有阶梯状图案 第二方向的第一端，在第二方向的第一端中共同连接到第一至第n半导体层的公共半导体层，第一至第n层选择晶体管，其从第一电极侧 第一电极和第一至第n存储器串以及使第i层选择晶体管（i为1至n之一）的第一至第n杂质区在第一端中的正常导通状态 第i个半导体层的第2方向。

公开(公告)号：US20120068241A1

公开(公告)日：2012-03-22

申请号：US13236734

申请日：2011-09-20

申请人： Kiwamu SAKUMA ,  Atsuhiro KINOSHITA

发明人： Kiwamu SAKUMA ,  Atsuhiro KINOSHITA

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L27/11578 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L29/785 ,  H01L29/792

摘要： According to one embodiment, a memory device includes first and second fin type stacked structures each includes first to i-th memory strings (i is a natural number except 1) that are stacked in a first direction, the first and second fin type stacked structures which extend in a second direction and which are adjacent in a third direction, a first portion connected to one end in the second direction of the first fin type stacked structure, a width in the third direction of the first portion being greater than a width in the third direction of the first fin type stacked structure, and a second portion connected to one end in the second direction of the second fin type stacked structure, a width in the third direction of the second portion being greater than a width in the third direction of the second fin type stacked structure.

摘要翻译： 根据一个实施例，存储器件包括第一和第二鳍式堆叠结构，每个第一和第二鳍式堆叠结构每个包括沿第一方向堆叠的第一至第i存储器串（i是除1之外的自然数），第一和第二鳍式堆叠结构 其在第二方向上延伸并且在第三方向上相邻，第一部分连接到第一鳍式堆叠结构的第二方向上的一端，第一部分的第三方向上的宽度大于第一方向上的宽度 第一鳍式堆叠结构的第三方向和与第二鳍式堆叠结构的第二方向的一端连接的第二部分，第二部分的第三方向上的宽度大于第三方向上的宽度 的第二鳍式堆叠结构。

公开(公告)号：US20130215670A1

公开(公告)日：2013-08-22

申请号：US13719775

申请日：2012-12-19

申请人： Masato ODA ,  Koichiro ZAITSU ,  Kiwamu SAKUMA ,  Shinichi YASUDA ,  Kohei OIKAWA

发明人： Masato ODA ,  Koichiro ZAITSU ,  Kiwamu SAKUMA ,  Shinichi YASUDA ,  Kohei OIKAWA

IPC分类号： G11C11/40

CPC分类号： G11C11/40 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0002 ,  G11C16/0441 ,  H03K19/1776

摘要： A memory circuit according to an embodiment includes: a plurality of memory cells each having one pair of first and second nonvolatile memory circuits, each of the first and second nonvolatile memory circuits in each memory cell being capable of making a transition between a high resistance state and a low resistance state, and in a state in which one memory cell in the plurality of memory cells has information stored therein, one of the first and second nonvolatile memory circuits in the one memory cell being in a high resistance state whereas the other being in a low resistance state.

摘要翻译： 根据实施例的存储器电路包括：多个存储单元，每个存储单元具有一对第一和第二非易失性存储器电路，每个存储单元中的每个第一和第二非易失性存储器电路能够在高电阻状态 和低电阻状态，并且在多个存储单元中的一个存储单元存储有信息的状态下，一个存储单元中的第一和第二非易失性存储器电路之一处于高电阻状态，而另一个存储单元 处于低电阻状态。

公开(公告)号：US20120068254A1

公开(公告)日：2012-03-22

申请号：US13072366

申请日：2011-03-25

申请人： Kiwamu SAKUMA ,  Atsuhiro Kinoshita

发明人： Kiwamu SAKUMA ,  Atsuhiro Kinoshita

IPC分类号： H01L29/792 ,  H01L21/308

CPC分类号： H01L29/792 ,  H01L27/11524 ,  H01L27/11551 ,  H01L29/7881

摘要： According to one embodiment, a memory device includes a semiconductor substrate, first, second, third and fourth fin-type stacked layer structures, each having memory strings stacked in a first direction perpendicular to a surface of the semiconductor substrate, and each extending to a second direction parallel to the surface of the semiconductor substrate, a first part connected to first ends in the second direction of the first and second fin-type stacked layer structures each other, a second part connected to first ends in the second direction of the third and fourth fin-type stacked layer structures each other, a third part connected to second ends in the second direction of the first and third fin-type stacked layer structures each other, and a fourth part connected to second ends in the second direction of the second and fourth fin-type stacked layer structures each other.

摘要翻译： 根据一个实施例，存储器件包括半导体衬底，第一，第二，第三和第四鳍式堆叠层结构，每个具有堆叠在垂直于半导体衬底的表面的第一方向上的存储串，并且每个延伸到 第二方向平行于半导体衬底的表面，第一部分连接到第一和第二鳍式堆叠层的第二方向上的第一端彼此结合，第二部分连接到第三端的第二端 第四鳍状堆叠层结构，第三部分与第一和第三鳍状堆叠层的第二方向的第二端部连接，第四部分与第二鳍片状堆叠层的第二方向的第二端部连接， 第二和第四鳍式堆叠层结构。