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    NONVOLATILE SEMICONDUCTOR MEMORY
    1.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY 失效
    非易失性半导体存储器

    公开(公告)号：US20120139030A1

    公开(公告)日：2012-06-07

    申请号：US13316603

    申请日：2011-12-12

    申请人： Kiwamu SAKUMA ,  Atsuhiro Kinoshita ,  Masahiro Kiyotoshi ,  Daisuke Hagishima ,  Koichi Muraoka

    发明人： Kiwamu SAKUMA ,  Atsuhiro Kinoshita ,  Masahiro Kiyotoshi ,  Daisuke Hagishima ,  Koichi Muraoka

    IPC分类号： H01L27/105 ,  H01L21/8239

    CPC分类号： H01L29/42328 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

    摘要： According to one embodiment, a nonvolatile semiconductor memory includes first to n-th (n is a natural number not less than 2) semiconductor layers in a first direction and extend in a second direction, and the semiconductor layers having a stair case pattern in a first end of the second direction, a common semiconductor layer connected to the first to n-th semiconductor layers commonly in the first end of the second direction, first to n-th layer select transistors which are provided in order from the first electrode side between the first electrode and the first to n-th memory strings, and first to n-th impurity regions which make the i-th layer select transistor (i is one of 1 to n) a normally-on state in the first end of the second direction of the i-th semiconductor layer.

    摘要翻译： 根据一个实施例，非易失性半导体存储器包括在第一方向上的第一至第n（n是不小于2的自然数）半导体层，并且在第二方向上延伸，并且半导体层具有阶梯状图案 第二方向的第一端，在第二方向的第一端中共同连接到第一至第n半导体层的公共半导体层，第一至第n层选择晶体管，其从第一电极侧 第一电极和第一至第n存储器串以及使第i层选择晶体管（i为1至n之一）的第一至第n杂质区在第一端中的正常导通状态 第i个半导体层的第2方向。

    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 失效
    半导体存储器件及其制造方法

    公开(公告)号：US20130032873A1

    公开(公告)日：2013-02-07

    申请号：US13326972

    申请日：2011-12-15

    申请人： Masahiro Kiyotoshi

    发明人： Masahiro Kiyotoshi

    IPC分类号： H01L29/792 ,  H01L21/28

    CPC分类号： H01L29/7926 ,  H01L27/11582

    摘要： According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, and a plurality of memory cells. The stacked body includes a plurality of stacked gate electrodes and inter-electrode insulating layers provided between the gate electrodes. The semiconductor pillar punches through the stacked body. The plurality of memory cells is provided in stacking direction. The memory cell includes a charge trap layer provided between the semiconductor pillar and the gate electrode via an air gap. The block insulating layer is provided between the charge trap layer and the gate electrode. Each of the plurality of memory cells is provided with a support portion configured to keep air gap distance between the charge trap layer and the semiconductor pillar.

    摘要翻译： 根据一个实施例，半导体存储器件包括堆叠体，半导体柱和多个存储单元。 层叠体包括设置在栅电极之间的多个层叠栅电极和电极间绝缘层。 半导体柱穿过堆叠体。 多个存储单元沿层叠方向设置。 存储单元包括通过气隙设置在半导体柱和栅电极之间的电荷陷阱层。 块绝缘层设置在电荷陷阱层和栅电极之间。 多个存储单元中的每一个设置有被配置为保持电荷陷阱层和半导体柱之间的气隙距离的支撑部分。

    Method for manufacturing a nonvolatile storage device
    9.
    发明授权
    Method for manufacturing a nonvolatile storage device 有权
    非易失性存储装置的制造方法

    公开(公告)号：US08143146B2

    公开(公告)日：2012-03-27

    申请号：US12469872

    申请日：2009-05-21

    申请人： Masahiro Kiyotoshi

    发明人： Masahiro Kiyotoshi

    IPC分类号： H01L21/20 ,  H01L21/36

    CPC分类号： G11C13/0004 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1675

    摘要： A method for manufacturing a nonvolatile storage device with a plurality of unit memory layers stacked therein is provided. Each of the unit memory layers includes: a first interconnect extending in a first direction; a second interconnect extending in a second direction; a recording unit sandwiched between the first and second interconnects and being capable of reversibly transitioning between a first state and a second state in response to a current supplied through the first and second interconnects; and a rectifying element sandwiched between the first interconnect and the recording unit and including at least one of p-type and n-type impurities. In the method, the first interconnect, the second interconnect, the recording unit, and a layer of an amorphous material including the at least one of p-type and n-type impurities used in the plurality of unit memory layers are formed at a temperature lower than a temperature at which the amorphous material is substantially crystallized. The amorphous material used in the plurality of unit memory layers is simultaneously crystallized and the impurities included in the amorphous material used in the plurality of unit memory layers are simultaneously activated.

    摘要翻译： 提供了一种制造具有堆叠在其中的多个单元存储层的非易失性存储装置的方法。 每个单元存储层包括：沿第一方向延伸的第一互连; 沿第二方向延伸的第二互连; 记录单元，夹在第一和第二互连之间，并且能够响应于通过第一和第二互连提供的电流在第一状态和第二状态之间可逆地转换; 以及夹在所述第一布线和所述记录单元之间并且包括p型和n型杂质中的至少一种的整流元件。 在该方法中，在多个单元存储层中使用的第一互连，第二互连，记录单元以及包含p型和n型杂质中的至少一种的非晶材料层形成在温度 低于无定形材料基本上结晶的温度。 在多个单元存储层中使用的非晶材料同时结晶化，并且包含在多个单元存储层中使用的非晶材料中的杂质同时被激活。

    Method of manufacturing semiconductor device
    10.
    发明授权
    Method of manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US08114755B2

    公开(公告)日：2012-02-14

    申请号：US12146143

    申请日：2008-06-25

    申请人： Ichiro Mizushima ,  Yoshio Ozawa ,  Takashi Nakao ,  Akihito Yamamoto ,  Takashi Suzuki ,  Masahiro Kiyotoshi ,  Minako Inukai ,  Kaori Umezawa ,  Hiroaki Yamada

    发明人： Ichiro Mizushima ,  Yoshio Ozawa ,  Takashi Nakao ,  Akihito Yamamoto ,  Takashi Suzuki ,  Masahiro Kiyotoshi ,  Minako Inukai ,  Kaori Umezawa ,  Hiroaki Yamada

    IPC分类号： H01L21/76

    CPC分类号： H01L21/764

    摘要： A method of manufacturing a semiconductor device includes removing a part of a semiconductor substrate to form a protruding portion and a recess portion in a surface area of the semiconductor substrate, forming a first epitaxial semiconductor layer in the recess portion, forming a second epitaxial semiconductor layer on the protruding portion and the first epitaxial semiconductor layer, removing a first part of the second epitaxial semiconductor layer with a second part of the second epitaxial semiconductor layer left to expose a part of the first epitaxial semiconductor layer, and etching the first epitaxial semiconductor layer from the exposed part of the first epitaxial semiconductor layer to form a cavity under the second part of the second epitaxial semiconductor layer.

    摘要翻译： 一种制造半导体器件的方法包括：去除半导体衬底的一部分以在半导体衬底的表面区域中形成突出部分和凹陷部分，在凹部中形成第一外延半导体层，形成第二外延半导体层 在所述突出部分和所述第一外延半导体层上，用所述第二外延半导体层的第二部分去除所述第二外延半导体层的第一部分，以露出所述第一外延半导体层的一部分，并且蚀刻所述第一外延半导体层 从第一外延半导体层的暴露部分形成在第二外延半导体层的第二部分下面的空腔。