利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

104 条记录 (耗时 0.024 秒)

    NONVOLATILE SEMICONDUCTOR MEMORY
    1.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY 失效
    非易失性半导体存储器

    公开(公告)号：US20120139030A1

    公开(公告)日：2012-06-07

    申请号：US13316603

    申请日：2011-12-12

    申请人： Kiwamu SAKUMA ,  Atsuhiro Kinoshita ,  Masahiro Kiyotoshi ,  Daisuke Hagishima ,  Koichi Muraoka

    发明人： Kiwamu SAKUMA ,  Atsuhiro Kinoshita ,  Masahiro Kiyotoshi ,  Daisuke Hagishima ,  Koichi Muraoka

    IPC分类号： H01L27/105 ,  H01L21/8239

    CPC分类号： H01L29/42328 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

    摘要： According to one embodiment, a nonvolatile semiconductor memory includes first to n-th (n is a natural number not less than 2) semiconductor layers in a first direction and extend in a second direction, and the semiconductor layers having a stair case pattern in a first end of the second direction, a common semiconductor layer connected to the first to n-th semiconductor layers commonly in the first end of the second direction, first to n-th layer select transistors which are provided in order from the first electrode side between the first electrode and the first to n-th memory strings, and first to n-th impurity regions which make the i-th layer select transistor (i is one of 1 to n) a normally-on state in the first end of the second direction of the i-th semiconductor layer.

    摘要翻译： 根据一个实施例，非易失性半导体存储器包括在第一方向上的第一至第n（n是不小于2的自然数）半导体层，并且在第二方向上延伸，并且半导体层具有阶梯状图案 第二方向的第一端，在第二方向的第一端中共同连接到第一至第n半导体层的公共半导体层，第一至第n层选择晶体管，其从第一电极侧 第一电极和第一至第n存储器串以及使第i层选择晶体管（i为1至n之一）的第一至第n杂质区在第一端中的正常导通状态 第i个半导体层的第2方向。

    MEMORY INCLUDING TRANSISTORS WITH DOUBLE FLOATING GATE STRUCTURES
    5.
    发明申请
    MEMORY INCLUDING TRANSISTORS WITH DOUBLE FLOATING GATE STRUCTURES 失效
    包含两个浮动门结构的晶体管的存储器

    公开(公告)号：US20130069134A1

    公开(公告)日：2013-03-21

    申请号：US13608436

    申请日：2012-09-10

    申请人： Tetsufumi TANAMOTO ,  Kosuke Tatsumura ,  Kiwamu Sakuma ,  Atsuhiro Kinoshita ,  Shinobu Fujita ,  Koichi Muraoka

    发明人： Tetsufumi TANAMOTO ,  Kosuke Tatsumura ,  Kiwamu Sakuma ,  Atsuhiro Kinoshita ,  Shinobu Fujita ,  Koichi Muraoka

    IPC分类号： H01L27/11

    CPC分类号： H01L29/42332 ,  G11C11/412 ,  G11C14/0063 ,  H01L27/1104 ,  H01L29/7881

    摘要： In a memory of an embodiment, first and second P-channel transistors are formed on a first semiconductor region, and each of the first and second P-channel transistors has a structure formed by stacking a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film, and a first control gate in this order on the first semiconductor region. In the memory, first and second N-channel transistors are formed on a second semiconductor region, and each of the first and second N-channel transistors has a structure formed by stacking a fourth insulating film, a third floating gate, a fifth insulating film, a fourth floating gate, a sixth insulating film, and a second control gate in this order on the second semiconductor region.

    摘要翻译： 在实施例的存储器中，第一和第二P沟道晶体管形成在第一半导体区域上，并且第一和第二P沟道晶体管中的每一个具有通过堆叠第一绝缘膜，第一浮动栅极， 第二绝缘膜，第二浮栅，第三绝缘膜和第一控制栅极。 在存储器中，第一和第二N沟道晶体管形成在第二半导体区域上，并且第一和第二N沟道晶体管中的每一个具有通过堆叠第四绝缘膜，第三浮栅，第五绝缘膜 ，第四浮栅，第六绝缘膜和第二控制栅极。

    Memory including transistors with double floating gate structures
    6.
    发明授权
    Memory including transistors with double floating gate structures 失效
    存储器包括具有双浮栅结构的晶体管

    公开(公告)号：US08610196B2

    公开(公告)日：2013-12-17

    申请号：US13608436

    申请日：2012-09-10

    申请人： Tetsufumi Tanamoto ,  Kosuke Tatsumura ,  Kiwamu Sakuma ,  Atsuhiro Kinoshita ,  Shinobu Fujita ,  Koichi Muraoka

    发明人： Tetsufumi Tanamoto ,  Kosuke Tatsumura ,  Kiwamu Sakuma ,  Atsuhiro Kinoshita ,  Shinobu Fujita ,  Koichi Muraoka

    IPC分类号： H01L27/11

    CPC分类号： H01L29/42332 ,  G11C11/412 ,  G11C14/0063 ,  H01L27/1104 ,  H01L29/7881

    摘要： In a memory of an embodiment, first and second P-channel transistors are formed on a first semiconductor region, and each of the first and second P-channel transistors has a structure formed by stacking a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film, and a first control gate in this order on the first semiconductor region. In the memory, first and second N-channel transistors are formed on a second semiconductor region, and each of the first and second N-channel transistors has a structure formed by stacking a fourth insulating film, a third floating gate, a fifth insulating film, a fourth floating gate, a sixth insulating film, and a second control gate in this order on the second semiconductor region.

    摘要翻译： 在实施例的存储器中，第一和第二P沟道晶体管形成在第一半导体区域上，并且第一和第二P沟道晶体管中的每一个具有通过堆叠第一绝缘膜，第一浮动栅极， 第二绝缘膜，第二浮栅，第三绝缘膜和第一控制栅极。 在存储器中，第一和第二N沟道晶体管形成在第二半导体区域上，并且第一和第二N沟道晶体管中的每一个具有通过堆叠第四绝缘膜，第三浮栅，第五绝缘膜 ，第四浮栅，第六绝缘膜和第二控制栅极。

    NONVOLATILE MEMORIES AND RECONFIGURABLE CIRCUITS
    7.
    发明申请
    NONVOLATILE MEMORIES AND RECONFIGURABLE CIRCUITS 有权
    非易失性存储器和可重新配置的电路

    公开(公告)号：US20120026779A1

    公开(公告)日：2012-02-02

    申请号：US13213871

    申请日：2011-08-19

    申请人： Kazutaka Ikegami ,  Atsuhiro Kinoshita ,  Daisuke Hagishima

    发明人： Kazutaka Ikegami ,  Atsuhiro Kinoshita ,  Daisuke Hagishima

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0002 ,  G11C2213/72 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/146 ,  H03K19/1776

    摘要： A nonvolatile memory according to an embodiment includes at least one memory cell including: a variable resistance memory comprising one end connected to a first terminal, and the other end connected to a second terminal, a drive voltage being applied to the first terminal; and a diode comprising a cathode connected to the second terminal, and an anode connected to a third terminal, a ground potential being applied to the third terminal. An output of the memory cell is output from the second terminal, the output of the memory cell depends on a resistance state of the variable resistance memory.

    摘要翻译： 根据实施例的非易失性存储器包括至少一个存储单元，包括：可变电阻存储器，包括连接到第一端子的一端，并且另一端连接到第二端子，施加到第一端子的驱动电压; 以及二极管，包括连接到第二端子的阴极和连接到第三端子的阳极，将地电位施加到第三端子。 存储单元的输出从第二端输出，存储单元的输出取决于可变电阻存储器的电阻状态。

    Nonvolatile programmable logic switches and semiconductor integrated circuit
    8.
    发明授权
    Nonvolatile programmable logic switches and semiconductor integrated circuit 失效
    非易失性可编程逻辑开关和半导体集成电路

    公开(公告)号：US08476690B2

    公开(公告)日：2013-07-02

    申请号：US13223331

    申请日：2011-09-01

    申请人： Daisuke Hagishima ,  Atsuhiro Kinoshita

    发明人： Daisuke Hagishima ,  Atsuhiro Kinoshita

    IPC分类号： G11C16/04 ,  H01L29/788

    CPC分类号： H01L29/788 ,  G11C16/0416 ,  G11C16/0466 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/11807

    摘要： A nonvolatile programmable logic switch according to an embodiment includes: a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type; a memory cell transistor including a first insulating film formed on the first semiconductor region, a charge storage film formed on the first insulating film, a second insulating film formed on the charge storage film, and a control gate formed on the second insulating film; a pass transistor including a third insulating film formed on the second semiconductor region, and a gate electrode formed on the third insulating film and electrically connected to the first drain region; a first electrode applying a substrate bias to the first semiconductor region, the first electrode being formed in the first semiconductor region; and a second electrode applying a substrate bias to the second semiconductor region, the second electrode being formed in the second semiconductor region.

    摘要翻译： 根据实施例的非易失性可编程逻辑开关包括：第一导电类型的第一半导体区域和第二导电类型的第二半导体区域; 存储单元晶体管，包括形成在第一半导体区域上的第一绝缘膜，形成在第一绝缘膜上的电荷存储膜，形成在电荷存储膜上的第二绝缘膜，以及形成在第二绝缘膜上的控制栅; 包括形成在第二半导体区域上的第三绝缘膜的通过晶体管和形成在第三绝缘膜上并电连接到第一漏极区的栅电极; 将第一电极施加到所述第一半导体区域的衬底偏压，所述第一电极形成在所述第一半导体区域中; 以及向所述第二半导体区域施加衬底偏压的第二电极，所述第二电极形成在所述第二半导体区域中。

    NONVOLATILE PROGRAMMABLE LOGIC SWITCHES AND SEMICONDUCTOR INTEGRATED CIRCUIT
    10.
    发明申请
    NONVOLATILE PROGRAMMABLE LOGIC SWITCHES AND SEMICONDUCTOR INTEGRATED CIRCUIT 失效
    非易失性可编程逻辑开关和半导体集成电路

    公开(公告)号：US20120061731A1

    公开(公告)日：2012-03-15

    申请号：US13223331

    申请日：2011-09-01

    申请人： Daisuke Hagishima ,  Atsuhiro Kinoshita

    发明人： Daisuke Hagishima ,  Atsuhiro Kinoshita

    IPC分类号： H01L27/092

    CPC分类号： H01L29/788 ,  G11C16/0416 ,  G11C16/0466 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/11807

    摘要： A nonvolatile programmable logic switch according to an embodiment includes: a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type; a memory cell transistor including a first insulating film formed on the first semiconductor region, a charge storage film formed on the first insulating film, a second insulating film formed on the charge storage film, and a control gate formed on the second insulating film; a pass transistor including a third insulating film formed on the second semiconductor region, and a gate electrode formed on the third insulating film and electrically connected to the first drain region; a first electrode applying a substrate bias to the first semiconductor region, the first electrode being formed in the first semiconductor region; and a second electrode applying a substrate bias to the second semiconductor region, the second electrode being formed in the second semiconductor region.

    摘要翻译： 根据实施例的非易失性可编程逻辑开关包括：第一导电类型的第一半导体区域和第二导电类型的第二半导体区域; 存储单元晶体管，包括形成在第一半导体区域上的第一绝缘膜，形成在第一绝缘膜上的电荷存储膜，形成在电荷存储膜上的第二绝缘膜，以及形成在第二绝缘膜上的控制栅; 包括形成在第二半导体区域上的第三绝缘膜的通过晶体管和形成在第三绝缘膜上并电连接到第一漏极区的栅电极; 将第一电极施加到所述第一半导体区域的衬底偏压，所述第一电极形成在所述第一半导体区域中; 以及向所述第二半导体区域施加衬底偏压的第二电极，所述第二电极形成在所述第二半导体区域中。