公开(公告)号：US07432731B2

公开(公告)日：2008-10-07

申请号：US11174009

申请日：2005-06-30

申请人： Kuljit S. Bains ,  Navneet Dour ,  Hany Fahmy ,  George Vergis ,  Christopher E. Cox

发明人： Kuljit S. Bains ,  Navneet Dour ,  Hany Fahmy ,  George Vergis ,  Christopher E. Cox

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008 ,  G11C2207/2254 ,  H04L25/0298

摘要： An embodiment may comprise memory with a memory array, a resistor coupled to a reference voltage, on die termination circuitry coupled with the resistor, and an input coupled to the on die termination circuitry and coupled with the memory array, the input to receive a calibration command to stop use of the input and the memory array and calibrate the on die termination circuitry with the resistor coupled to the reference voltage. Other embodiments are disclosed herein.

摘要翻译： 实施例可以包括具有存储器阵列的存储器，耦合到参考电压的电阻器，与电阻器耦合的管芯端接电路上，以及耦合到管芯端接电路并与存储器阵列耦合的输入端，用于接收校准 命令停止使用输入和存储器阵列，并用耦合到参考电压的电阻校准芯片上的端接电路。 本文公开了其它实施例。

公开(公告)号：US20160292119A1

公开(公告)日：2016-10-06

申请号：US15068128

申请日：2016-03-11

申请人： Christopher E. Cox ,  Kuljit S. Bains

发明人： Christopher E. Cox ,  Kuljit S. Bains

IPC分类号： G06F13/40 ,  G06F11/34 ,  G06F11/30

CPC分类号： G06F13/4068 ,  G06F11/2221 ,  G06F11/3027 ,  G06F11/3051 ,  G06F11/3089 ,  G06F11/349 ,  G06F13/385 ,  G06F13/4022

摘要： Techniques and mechanisms for configuring an integrated circuit to couple to, and exchange data with, a hardware interface. In an embodiment, the integrated circuit comprises a data channel including a plurality of bits, configuration logic, and a plurality of contacts including a first contact group and a second contact group. In response to a signal indicating connectivity of the integrated circuit to the interface, a mode of the configuration logic is selected to couple the plurality of bits to one of the first contact group and the second contact group.

公开(公告)号：US09317464B2

公开(公告)日：2016-04-19

申请号：US14316554

申请日：2014-06-26

申请人： Christopher E. Cox ,  Kuljit S. Bains

发明人： Christopher E. Cox ,  Kuljit S. Bains

IPC分类号： G06F3/00 ,  G06F13/12 ,  G06F13/38 ,  G06F11/30 ,  G06F11/22

CPC分类号： G06F13/4068 ,  G06F11/2221 ,  G06F11/3027 ,  G06F11/3051 ,  G06F11/3089 ,  G06F11/349 ,  G06F13/385 ,  G06F13/4022

摘要： Techniques and mechanisms for configuring an integrated circuit to couple to, and exchange data with, a hardware interface. In an embodiment, the integrated circuit comprises a data channel including a plurality of bits, configuration logic, and a plurality of contacts including a first contact group and a second contact group. In response to a signal indicating connectivity of the integrated circuit to the interface, a mode of the configuration logic is selected to couple the plurality of bits to one of the first contact group and the second contact group.

摘要翻译： 用于配置集成电路以耦合到硬件接口并与硬件接口交换数据的技术和机制。 在一个实施例中，集成电路包括包括多个位，配置逻辑和包括第一接触组和第二接触组的多个触点的数据通道。 响应于指示集成电路到接口的连通性的信号，选择配置逻辑的模式以将多个位耦合到第一接触组和第二接触组中的一个。

公开(公告)号：US20150378950A1

公开(公告)日：2015-12-31

申请号：US14316554

申请日：2014-06-26

申请人： Christopher E. Cox ,  Kuljit S. Bains

发明人： Christopher E. Cox ,  Kuljit S. Bains

IPC分类号： G06F13/38 ,  G06F11/22 ,  G06F11/30

CPC分类号： G06F13/4068 ,  G06F11/2221 ,  G06F11/3027 ,  G06F11/3051 ,  G06F11/3089 ,  G06F11/349 ,  G06F13/385 ,  G06F13/4022

摘要： Techniques and mechanisms for configuring an integrated circuit to couple to, and exchange data with, a hardware interface. In an embodiment, the integrated circuit comprises a data channel including a plurality of bits, configuration logic, and a plurality of contacts including a first contact group and a second contact group. In response to a signal indicating connectivity of the integrated circuit to the interface, a mode of the configuration logic is selected to couple the plurality of bits to one of the first contact group and the second contact group.

摘要翻译： 用于配置集成电路以耦合到硬件接口并与硬件接口交换数据的技术和机制。 在一个实施例中，集成电路包括包括多个位，配置逻辑和包括第一接触组和第二接触组的多个触点的数据通道。 响应于指示集成电路到接口的连通性的信号，选择配置逻辑的模式以将多个位耦合到第一接触组和第二接触组中的一个。

公开(公告)号：US09396784B2

公开(公告)日：2016-07-19

申请号：US13997959

申请日：2012-03-27

申请人： Christopher E. Cox ,  Kuljit S. Bains ,  John B. Halbert

发明人： Christopher E. Cox ,  Kuljit S. Bains ,  John B. Halbert

IPC分类号： G11C16/24 ,  G11C11/406 ,  G11C11/4074

CPC分类号： G11C11/40615 ,  G11C7/00 ,  G11C7/08 ,  G11C11/40611 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4096 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3418 ,  G11C2211/4065 ,  G11C2211/4068

摘要： Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging of voltage levels representing stored data when read/write operations are idle. At least one register source provides a first voltage level and a second voltage level that is less than the first voltage level. With such a configuration, during the active mode, the memory device operates at the first voltage level as provided by the at least one register source, and during the self-refresh mode, the memory device operates at the second voltage level as provided by the at least one register source.

摘要翻译： 设备，系统和方法包括适应存储器件的读/写操作和自刷新模式的主动模式，以适应当读/写操作空闲时表示存储数据的电压电平的再充电。 至少一个寄存器源提供小于第一电压电平的第一电压电平和第二电压电平。 通过这样的配置，在活动模式期间，存储器件以由至少一个寄存器源提供的第一电压电平工作，并且在自刷新模式期间，存储器件以由第二电压电平 至少一个寄存器源。

公开(公告)号：US20160092383A1

公开(公告)日：2016-03-31

申请号：US14498806

申请日：2014-09-26

申请人： Kuljit S. Bains ,  Nadav Bonen ,  Christopher E. Cox ,  James A. McCall

发明人： Kuljit S. Bains ,  Nadav Bonen ,  Christopher E. Cox ,  James A. McCall

IPC分类号： G06F13/28 ,  G06F13/16

CPC分类号： G06F13/287 ,  G06F13/1678

摘要： A memory device and a memory controller can interface over a system data bus that has a narrower bandwidth than a data bus internal to the memory device. The memory device and memory controller transfer data over the system data bus on all transfer periods of a burst length, but send fewer bits than would be needed for the exchange to transfer all bits that can be read or written on the internal data bus of the memory device. The memory device can have different operating modes to allow for a common memory device to be used in different system configurations based on the ability to interface with the narrower bandwidth system data bus.

摘要翻译： 存储器设备和存储器控制器可以通过比存储器件内部的数据总线窄的带宽的系统数据总线进行接口。 存储器设备和存储器控制器在突发长度的所有传输周期上通过系统数据总线传送数据，但是发送比用于传送所有可以读取或写入内部数据总线上的所有位的位少的位 存储设备。 存储器设备可以具有不同的操作模式，以允许基于与较窄带宽系统数据总线接口的能力在不同系统配置中使用公共存储器设备。

公开(公告)号：US20080197877A1

公开(公告)日：2008-08-21

申请号：US11708148

申请日：2007-02-16

申请人： Christopher E. Cox ,  Hany Fahmy ,  Hideo Oie

发明人： Christopher E. Cox ,  Hany Fahmy ,  Hideo Oie

IPC分类号： H03K19/173

CPC分类号： G11C7/1045 ,  G11C11/4072 ,  G11C11/4076

摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for per byte lane dynamic on-die termination. In some embodiments, an integrated circuit includes logic to independently program at least one on-die termination (ODT) value for each of a plurality of integrated circuits coupled together through an interconnect. Other embodiments are described and claimed.

摘要翻译： 本发明的实施例一般涉及用于每字节通道动态片上终端的系统，方法和装置。 在一些实施例中，集成电路包括用于独立地编程通过互连耦合在一起的多个集成电路中的每一个的至少一个片上终端（ODT）值的逻辑。 描述和要求保护其他实施例。

公开(公告)号：US20190245309A1

公开(公告)日：2019-08-08

申请号：US16389781

申请日：2019-04-19

申请人： Jaejin Lee ,  Jun Liao ,  Xiang Li ,  George Vergis ,  Christopher E. Cox

发明人： Jaejin Lee ,  Jun Liao ,  Xiang Li ,  George Vergis ,  Christopher E. Cox

IPC分类号： H01R13/6471 ,  H05K5/00 ,  H05K5/02 ,  H05K1/18 ,  H01R12/73

CPC分类号： H01R13/6471 ,  H01R12/73 ,  H05K1/18 ,  H05K5/0069 ,  H05K5/0247 ,  H05K2201/10159 ,  H05K2201/10189

摘要： Embodiments of the present disclosure relate to a connector to connect a printed circuit board (PCB) with a memory device, where the connector includes a housing couplable with the PCB; a first signal pin coupled with the housing, where the first signal pin includes a first portion that includes a first curve, and a second portion that extends from the first portion and includes a second curve; and a second signal pin coupled with the housing, where the second signal pin includes a third portion that includes a third curve, and a fourth portion that extends from the third portion and includes a fourth curve, where the first curve is curved in a first opposite direction relative to the third curve, and where the second curve is curved in a second opposite direction relative to the fourth curve.

公开(公告)号：US20150234726A1

公开(公告)日：2015-08-20

申请号：US14578191

申请日：2014-12-19

申请人： Brian P. Moran ,  Konika Ganguly ,  Rebecca Z. Loop ,  Xiang Li ,  Christopher E. Cox

发明人： Brian P. Moran ,  Konika Ganguly ,  Rebecca Z. Loop ,  Xiang Li ,  Christopher E. Cox

IPC分类号： G06F11/30 ,  G06F13/40

CPC分类号： G06F13/4081 ,  G06F13/1694 ,  Y02D10/14 ,  Y02D10/151

摘要： Techniques and mechanisms to exchange communications via a printed circuit board (PCB) between a processor device and a memory device. In an embodiment, the processor device is configured based on a memory type of the memory device to an interface mode of multiple interface modes each corresponding to a different respective one of multiple memory standards. A voltage regulator (VR) is programmed, based on the memory type, to a VR mode to provide one or more voltages to the memory device via a hardware interface on the PCB. In another embodiment, x signal lines of an interconnect disposed in or on the PCB are each coupled between the processor device and the memory device to one another. The value x is an integer equal to a total number of signals of a superset of sets of signals each specified by a different respective one of the multiple memory standards.

摘要翻译： 通过处理器设备和存储设备之间的印刷电路板（PCB）交换通信的技术和机制。 在一个实施例中，处理器设备基于存储器设备的存储器类型被配置为多个接口模式的接口模式，每个接口模式对应于多个存储器标准中的不同相应的一个存储器标准。 基于存储器类型将电压调节器（VR）编程为VR模式，以经由PCB上的硬件接口向存储器件提供一个或多个电压。 在另一个实施例中，布置在PCB中或PCB上的互连的x个信号线各自彼此耦合在处理器设备和存储器件之间。 值x是等于由多个存储器标准中的不同的相应一个指定的信号组的超集的信号的总数的整数。

公开(公告)号：US08118483B2

公开(公告)日：2012-02-21

申请号：US11472823

申请日：2006-06-21

申请人： Christopher E. Cox

发明人： Christopher E. Cox

IPC分类号： G01K7/00 ,  G01K15/00

CPC分类号： G01K1/00 ,  G01K7/425 ,  G01K2215/00 ,  G06F1/206 ,  G06F1/32 ,  G06F11/3034 ,  G06F11/3037 ,  G06F11/3093 ,  H01L2924/0002 ,  Y02D10/16 ,  H01L2924/00

摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for thermal sensor power savings using a toggle control. In some embodiments, an integrated circuit (e.g., a memory device) includes an on-die thermal sensor, a storage element (e.g., a register), and toggle logic. The toggle logic may transition the thermal sensor from a first power consumption level to a second power consumption level responsive, at least in part, to a toggle indication.

摘要翻译： 本发明的实施例一般涉及使用肘节控制的热传感器功率节省的系统，方法和装置。 在一些实施例中，集成电路（例如，存储器件）包括管芯上的热传感器，存储元件（例如，寄存器）和切换逻辑。 触发逻辑可以将热传感器从第一功率消耗水平转换到第二功率消耗水平，至少部分地响应于触发指示。