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公开(公告)号：US06629191B1
公开(公告)日：2003-09-30
申请号：US09340140
申请日：1999-06-28
IPC分类号： G06F1206
CPC分类号： G06F12/0246 , G06F2212/7211
摘要： In a memory including a flash memory, the life of the memory is prevented from being decreased due to the high frequency of rewrite operations of data to a specific area. When the erasure frequency of a block 301, storing four sectors of data, is high, each sector of block 301 is transferred to different blocks 302-305 to avoid deterioration of the data of block 301 due to the high frequency of rewriting.
摘要翻译： 在包括闪速存储器的存储器中，由于将数据重写到特定区域的高频率，防止存储器的寿命减少。 当存储四个数据扇区的块301的擦除频率高时，块301的每个扇区被传送到不同的块302-305，以避免由于重写的高频而导致块301的数据的劣化。
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公开(公告)号：USRE45857E1
公开(公告)日：2016-01-19
申请号：US13475679
申请日：2012-05-18
CPC分类号： G06F11/1008
摘要： A storage device, including: a non-volatile semiconductor memory which is electrically erasable; a system interface coupled with an external host system; and a controller reading data from the non-volatile semiconductor memory and transmitting data to the host system via the system interface in response to a read command received by the system interface from the host system; and wherein the controller starts reading (N+n)th sector data from the non-volatile semiconductor memory, while the controller transmits Nth sector data that has been read from the non-volatile semiconductor memory to the host system via the system interface, in response to the read command for successive sector data.
摘要翻译： 一种存储装置，包括：电可擦除的非易失性半导体存储器; 与外部主机系统耦合的系统接口; 以及控制器，从所述非易失性半导体存储器读取数据，并且响应于所述系统接口从所述主机系统接收到的读取命令，经由所述系统接口向所述主机系统发送数据; 并且其中所述控制器从所述非易失性半导体存储器开始读取第（N + n）个扇区数据，同时所述控制器经由所述系统接口将从所述非易失性半导体存储器读取的第N个扇区数据发送到所述主机系统， 对连续扇区数据的读命令作出响应。
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公开(公告)号：US08064257B2
公开(公告)日：2011-11-22
申请号：US12615502
申请日：2009-11-10
申请人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
发明人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
IPC分类号： G11C11/34
CPC分类号： G11C16/349 , G11C29/76 , G11C29/88
摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.
摘要翻译： 响应于由用于访问存储在所述非易失性半导体存储器中的多个数据块的系统接口单元接收到的读取命令，控制器对来自非易失性半导体存储器的两个存储器执行数据块的选择性读取操作 。 所述控制器还执行数据的并行操作，所述数据传输已经经过错误校正单元的错误检测和纠错操作的第一数据块经由所述系统接口单元从所述两个存储器之一传送到主机系统，并且 将要进行错误检测和纠错操作的第二数据块的数据传输从所述非易失性半导体存储器传输到两个存储器中的另一个。
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4.发明申请Electrically alterable non-volatile multi-level memory device and method of operating such a device 失效电动式可变非易失性多级存储装置及其操作方法公开(公告)号：US20050128819A1
公开(公告)日：2005-06-16
申请号：US11043114
申请日：2005-01-27
CPC分类号： G11C16/28 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/30 , G11C2211/5621 , G11C2211/5632 , G11C2211/5634 , G11C2211/5641 , G11C2211/5642
摘要： An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cell to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.
摘要翻译： 一种可电气可变的非易失性多级存储器件和操作这种器件的方法，其包括将存储器单元中的至少一个的状态设置为从包括至少第一至第四电平状态的多个状态中选择的一种状态 响应于要存储在一个存储器单元中的信息，并且通过利用在第二和第二电平状态之间设置的第一参考电平来读取存储单元的状态来确定读出状态是否对应于第一至第四电平状态之一 第三电平状态，在第一和第二电平状态之间设置的第二参考电平和在第三和第四电平状态之间设置的第三参考电平。
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5.发明授权Semiconductor memory having electrically erasable and programmable semiconductor memory cells 失效具有电可擦除和可编程的半导体存储器单元的半导体存储器公开(公告)号：US06891759B2
公开(公告)日：2005-05-10
申请号：US10872515
申请日：2004-06-22
CPC分类号： G11C16/28 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/30 , G11C2211/5621 , G11C2211/5632 , G11C2211/5634 , G11C2211/5641 , G11C2211/5642
摘要： A method of operating an electrically alterable non-volatile multi-level memory device includes settling a status of at least one of the memory cell to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.
摘要翻译： 一种操作电可更改的非易失性多级存储器件的方法包括：将存储器单元中的至少一个的状态设置为从包括至少第一至第四电平状态的多个状态中选择的一个状态， 存储在一个存储器单元中，并且通过利用在第二和第三电平状态之间设置的第一参考电平来读取存储器单元的状态来确定读出状态是否对应于第一至第四电平状态之一，第二 在第一和第二电平状态之间设置的参考电平和在第三和第四电平状态之间设置的第三参考电平。
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6.发明授权Semiconductor memory having electrically erasable and programmable nonvolatile semiconductor memory cells 有权具有电可擦除和可编程的非易失性半导体存储单元的半导体存储器公开(公告)号：US06493273B2
公开(公告)日：2002-12-10
申请号：US09944406
申请日：2001-09-04
IPC分类号： G11C700
CPC分类号： G11C16/28 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/30 , G11C2211/5621 , G11C2211/5632 , G11C2211/5634 , G11C2211/5641 , G11C2211/5642
摘要： A semiconductor memory includes a memory block consisting of a plurality of cells, a write control section, and a read control section. The write control section sets a potential to each of the plurality of cells in such a manner that the potential corresponds to a level indicated by a bit data string obtained by arranging pieces of bit data which are stored in buffers A and B and which are to be stored in the cell in the order of the buffer A and the buffer B. The read control section has a discriminator corresponding to each of the plurality of cells. The discriminator sets a threshold voltage to a potential level that corresponds to a number of discriminating operations to be performed with respect to a corresponding cell and a result of a discriminating operation already performed with respect to the cell. As a result of these operations, the semiconductor memory can determine the pieces of bit data in the order of the buffer A and the buffer B every time the discriminating operation is performed with respect to the cell.
摘要翻译： 半导体存储器包括由多个单元组成的存储块，写入控制部分和读取控制部分。 写入控制部分以这样一种方式设置多个单元中的每一个的电位，使得该电位对应于通过布置存储在缓冲器A和B中的位数据而得到的位数据串所指示的电平， 以缓冲器A和缓冲器B的顺序存储在单元中。读取控制部分具有与多个单元中的每一个对应的鉴别器。 鉴别器将阈值电压设置为对应于相对于相应小区执行的识别操作的数量的电位电平和相对于该单元执行的鉴别操作的结果。 作为这些操作的结果，半导体存储器可以在每次对单元执行鉴别操作时，以缓冲器A和缓冲器B的顺序来确定位数据。
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公开(公告)号：US06459644B2
公开(公告)日：2002-10-01
申请号：US09779610
申请日：2001-02-09
IPC分类号： G11C800
CPC分类号： G06F3/0601 , G06F12/0246 , G06F12/04 , G06F2003/0694 , G11C16/349
摘要： In the present invention, disclosed is a semiconductor memory device capable of reducing the number of erasing times of each block allocated to a cluster or the number of blocks to be erased in one writing to the minimum. As an embodiment of the present invention, when a host system 1 performs accessing, for each cluster as a unit, to the FAT partition prepared on a flash memory 17 of the semiconductor memory device 100, a CPU 6 adds an address offset value held by address offset storage section 10 to a logical address specified by the host system 1, whereby a logical address of a head sector of the cluster correspond to a physical address of a head sector of a unit block for erasing/writing data in the flash memory 17.
摘要翻译： 在本发明中，公开了一种半导体存储装置，其能够将分配给群集的每个块的擦除次数或一次写入中要擦除的块的数量减少到最小。 作为本发明的一个实施例，当主机系统1以每个集群为单位执行对在半导体存储装置100的闪速存储器17上准备的FAT分区的访问时，CPU6将由 地址偏移存储部分10分配给由主机系统1指定的逻辑地址，由此簇的头扇区的逻辑地址对应于用于擦除/写入闪速存储器17中的数据的单元块的头扇区的物理地址 。
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公开(公告)号：US06339546B1
公开(公告)日：2002-01-15
申请号：US09662926
申请日：2000-09-15
IPC分类号： G11C1606
CPC分类号： G06F11/1666 , G06F11/1008 , G06F11/1048 , G06F11/1068 , G06F2201/88 , G11C29/42 , G11C29/76 , G11C2029/0411 , G11C2029/1208
摘要： A semiconductor storage device that determines the cause of an error at the time of the error correction of data read out from a non-volatile semiconductor memory, on the basis of a previously recorded error correction count, and selects a data refresh processing or a substitute processing to perform. When the error is detected, the corrected data is rewritten back for preventing reoccurrence of error due to accidental cause. If it is determined that the reoccurrence frequency of the error is high and the error is due to degradation of the storage medium, based on the error correction count, the substitute processing is performed.
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公开(公告)号：US06223311B1
公开(公告)日：2001-04-24
申请号：US09432389
申请日：1999-11-02
IPC分类号： G11C2900
CPC分类号： G11C29/028 , G11C16/04 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C29/50016
摘要： In a memory device using an electrically rewritable nonvolatile memory as a storage medium, wherein, in order to allow the memory to deteriorate evenly, the erasing time and writing time are measured, the influence of scatter of cells in the memory being eliminated on the basis of the resultant measurement values, a substantial degree of deterioration being thereby determined with a high accuracy, whereby a memory device of a high reliability and a high efficiency is practically obtained. In order to rewrite an electrically rewritable nonvolatile memory (1), there are provided a means for measuring the erasing time and writing time, a means for comparing an erasing time with a stored reference time, a means for correcting writing time on the basis of the results of the comparison, and a means for determining deterioration on the basis of the results of the correction. According to the present invention, the substantial deterioration of each cell can be determined, and such control is possible that more deteriorated memory is used less frequently while less deteriorated memory is used more frequently. As a result, the reliability of the memory is improved, and the memory can have a longer service life.
摘要翻译： 在使用电可重写非易失性存储器作为存储介质的存储装置中，为了使存储器均匀地劣化，测量擦除时间和写入时间，基于消除了存储器中的单元的散射的影响 所得到的测量值，由此以高精度确定了相当程度的劣化，从而实际上获得了高可靠性和高效率的存储器件。 为了重写可重写的非易失性存储器（1），提供了一种用于测量擦除时间和写入时间的装置，用于将擦除时间与存储的基准时间进行比较的装置，用于基于 比较结果，以及根据校正结果确定劣化的方法。 根据本发明，可以确定每个单元的实质性劣化，并且可以更频繁地使用较少劣化的存储器，因此可以更少地使用更恶化的存储器，并且可以进行这种控制。 结果，提高了存储器的可靠性，并且存储器可以具有更长的使用寿命。
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公开(公告)号：US5978941A
公开(公告)日：1999-11-02
申请号：US913338
申请日：1997-09-11
CPC分类号： G11C16/3495 , G11C16/14 , G11C16/349 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C29/50016 , G11C29/52 , G11C29/56012 , G11C16/04
摘要： In a memory device using an electrically rewritable nonvolatile memory as a storage medium, wherein, in order to allow the memory to deteriorate evenly, the erasing time and writing time are measured, the influence of scatter of cells in the memory being eliminated on the basis of the resultant measurement values, a substantial degree of deterioration being thereby determined with a high accuracy, whereby a memory device of a high reliability and a high efficiency is practically obtained. In order to rewrite an electrically rewritable nonvolatile memory (1), there are provided a means for measuring the erasing time and writing time, a means for comparing an erasing time with a stored reference time, a means for correcting writing time on the basis of the results of the comparison, and a means for determining deterioration on the basis of the results of the correction. According to the present invention, the substantial deterioration of each cell can be determined, and such control is possible that more deteriorated memory is used less frequently while less deteriorated memory is used more frequently. As a result, the reliability of the memory is improved, and the memory can have a longer service life.
摘要翻译： PCT No.PCT / JP95 / 00429 Sec。 371日期：1997年9月11日 102（e）1997年9月11日PCT 1995年3月15日PCT PCT。 出版物WO96 / 28826 日期1996年9月19日在使用电可重写非易失性存储器作为存储介质的存储器件中，为了使存储器均匀地劣化，测量擦除时间和写入时间，存储器中的单元散射的影响 基于所得到的测量值消除，从而以高精度确定了显着的劣化程度，从而实际上获得了高可靠性和高效率的存储器件。 为了重写可重写的非易失性存储器（1），提供了一种用于测量擦除时间和写入时间的装置，用于将擦除时间与存储的基准时间进行比较的装置，用于基于 比较结果，以及根据校正结果确定劣化的方法。 根据本发明，可以确定每个单元的实质性劣化，并且可以更频繁地使用较少劣化的存储器，因此可以更少地使用更恶化的存储器，并且可以进行这种控制。 结果，提高了存储器的可靠性，并且存储器可以具有更长的使用寿命。
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