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    Gate structure, semiconductor memory device having the gate structure and methods of fabricating the same
    2.
    发明申请
    Gate structure, semiconductor memory device having the gate structure and methods of fabricating the same 审中-公开
    门结构，具有栅极结构的半导体存储器件及其制造方法

    公开(公告)号：US20100109074A1

    公开(公告)日：2010-05-06

    申请号：US12654029

    申请日：2009-12-08

    申请人： Kwang-Soo Seol ,  Byung-Kl Kim ,  Eun-Kyung Lee ,  Yo-Sep Min ,  Kyung-Sang Cho ,  Jae-Ho Lee ,  Jae-Young Choi

    发明人： Kwang-Soo Seol ,  Byung-Kl Kim ,  Eun-Kyung Lee ,  Yo-Sep Min ,  Kyung-Sang Cho ,  Jae-Ho Lee ,  Jae-Young Choi

    IPC分类号： H01L29/792

    CPC分类号： H01L29/42332 ,  B82Y10/00 ,  H01L29/40114 ,  H01L29/42348

    摘要： A gate structure using nanodots as a trap site, a semiconductor device having the gate structure and methods of fabricating the same are provided. The gate structure may include a tunneling layer, a plurality of nanodots on the tunneling layer, and a control insulating layer including a high-k dielectric layer on the tunneling layer and the nanodots. A semiconductor memory device may further include a semiconductor substrate, the gate structure according to example embodiments on the semiconductor substrate and a first impurity region and a second impurity region in the semiconductor substrate, wherein the gate structure is in contact with the first and second impurity regions.

    摘要翻译： 提供了使用纳米点作为陷阱位置的栅极结构，具有栅极结构的半导体器件及其制造方法。 栅极结构可以包括隧道层，隧道层上的多个纳米点，以及在隧道层和纳米点上包括高k电介质层的控制绝缘层。 半导体存储器件还可以包括半导体衬底，半导体衬底上的示例性实施例的栅极结构和半导体衬底中的第一杂质区和第二杂质区，其中栅极结构与第一和第二杂质接触 地区。

    Memory device and method of manufacturing the same
    3.
    发明申请
    Memory device and method of manufacturing the same 审中-公开
    存储器件及其制造方法

    公开(公告)号：US20070202648A1

    公开(公告)日：2007-08-30

    申请号：US11652583

    申请日：2007-01-12

    申请人： Seong Jae Choi ,  Kwang Soo Seol ,  Jae-Young Choi ,  Dong-Kee Yi ,  Seon Mi Yoon

    发明人： Seong Jae Choi ,  Kwang Soo Seol ,  Jae-Young Choi ,  Dong-Kee Yi ,  Seon Mi Yoon

    IPC分类号： H01L21/336

    CPC分类号： B82Y10/00 ,  H01L29/40114

    摘要： Provided is a memory device comprising a substrate, a source region, and a drain region that may be formed in the substrate and spaced apart from each other, a memory cell that may be formed on the surface of the substrate, connecting the source region and the drain region, and including a plurality of nanocrystals, wherein the memory cell comprises a first tunneling oxide layer formed on the substrate, and a control oxide layer including a plurality of nanocrystals formed on the tunneling oxide layer and a control gate formed on the memory cell. The memory device may include a polyelectrolyte film which enables a uniform arrangement of nanocrystals. The device characteristics may be controlled and a memory device with improved device characteristics may be provided.

    摘要翻译： 提供了一种存储器件，其包括可以形成在衬底中并彼此间隔开的衬底，源区和漏区，可以形成在衬底的表面上的存储单元，连接源区和 漏极区域，并且包括多个纳米晶体，其中所述存储单元包括形成在所述衬底上的第一隧道氧化物层，以及包括形成在所述隧道氧化物层上的多个纳米晶体的控制氧化物层和形成在所述存储器上的控制栅极 细胞。 存储器件可以包括能够均匀排列纳米晶体的聚电解质膜。 可以控制器件特性，并且可以提供具有改进的器件特性的存储器件。

    Chemical mechanical polishing pad with micro-mold and production method thereof
    7.
    发明申请
    Chemical mechanical polishing pad with micro-mold and production method thereof 审中-公开
    化学机械抛光垫用微型模具及其制造方法

    公开(公告)号：US20060068088A1

    公开(公告)日：2006-03-30

    申请号：US10952292

    申请日：2004-09-28

    申请人： Hae-Do Jeong ,  Jae-Young Choi ,  Hyoung-Jae Kim ,  Heon-Deok Seo ,  Boum-Young Park ,  Jae-Hong Park

    发明人： Hae-Do Jeong ,  Jae-Young Choi ,  Hyoung-Jae Kim ,  Heon-Deok Seo ,  Boum-Young Park ,  Jae-Hong Park

    IPC分类号： B28B7/38

    CPC分类号： B24B37/26 ,  B24D18/0009

    摘要： The present invention relates to a chemical mechanical polishing (CMP) pad with a micro-mold, and a production method thereof. More particularly, the present invention relates to a CMP pad with a micro-mold, in which the surface of the CMP pad is uniformly formed so as to avoid the glazing of the polishing pad, prevent a change in slurry flow and maintain the contact area between the polishing pad and a semiconductor wafer constant, thus allowing the wafer to be polished in a continuous and stable manner, and permitting the semiconductor wafer to be polished into the desired shape, as well as a production method thereof.

    摘要翻译： 本发明涉及具有微型模具的化学机械抛光（CMP）垫及其制造方法。 更具体地说，本发明涉及一种具有微模的CMP垫，其中CMP垫的表面均匀地形成，以避免抛光垫的上光，防止浆料流动的变化并保持接触面积 在抛光垫和半导体晶片之间恒定，从而允许晶片以连续且稳定的方式被抛光，并且允许半导体晶片被抛光成所需的形状，以及其制造方法。