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    Gate structure, semiconductor memory device having the gate structure and methods of fabricating the same
    1.
    发明申请
    Gate structure, semiconductor memory device having the gate structure and methods of fabricating the same 审中-公开
    门结构，具有栅极结构的半导体存储器件及其制造方法

    公开(公告)号：US20100109074A1

    公开(公告)日：2010-05-06

    申请号：US12654029

    申请日：2009-12-08

    申请人： Kwang-Soo Seol ,  Byung-Kl Kim ,  Eun-Kyung Lee ,  Yo-Sep Min ,  Kyung-Sang Cho ,  Jae-Ho Lee ,  Jae-Young Choi

    发明人： Kwang-Soo Seol ,  Byung-Kl Kim ,  Eun-Kyung Lee ,  Yo-Sep Min ,  Kyung-Sang Cho ,  Jae-Ho Lee ,  Jae-Young Choi

    IPC分类号： H01L29/792

    CPC分类号： H01L29/42332 ,  B82Y10/00 ,  H01L29/40114 ,  H01L29/42348

    摘要： A gate structure using nanodots as a trap site, a semiconductor device having the gate structure and methods of fabricating the same are provided. The gate structure may include a tunneling layer, a plurality of nanodots on the tunneling layer, and a control insulating layer including a high-k dielectric layer on the tunneling layer and the nanodots. A semiconductor memory device may further include a semiconductor substrate, the gate structure according to example embodiments on the semiconductor substrate and a first impurity region and a second impurity region in the semiconductor substrate, wherein the gate structure is in contact with the first and second impurity regions.

    摘要翻译： 提供了使用纳米点作为陷阱位置的栅极结构，具有栅极结构的半导体器件及其制造方法。 栅极结构可以包括隧道层，隧道层上的多个纳米点，以及在隧道层和纳米点上包括高k电介质层的控制绝缘层。 半导体存储器件还可以包括半导体衬底，半导体衬底上的示例性实施例的栅极结构和半导体衬底中的第一杂质区和第二杂质区，其中栅极结构与第一和第二杂质接触 地区。

    Gate structure including multi-tunneling layer and method of fabricating the same, non-volatile memory device and method of fabricating the same
    3.
    发明申请
    Gate structure including multi-tunneling layer and method of fabricating the same, non-volatile memory device and method of fabricating the same 审中-公开
    包括多隧道层的栅结构及其制造方法，非易失性存储器件及其制造方法

    公开(公告)号：US20070114572A1

    公开(公告)日：2007-05-24

    申请号：US11600737

    申请日：2006-11-17

    申请人： Kwang-Soo Seol ,  Woong-Chul Shin ,  Byung Kim ,  Eun-Kyung Lee ,  Kyung-Sang Cho

    发明人： Kwang-Soo Seol ,  Woong-Chul Shin ,  Byung Kim ,  Eun-Kyung Lee ,  Kyung-Sang Cho

    IPC分类号： H01L29/76

    CPC分类号： H01L29/42332 ,  B82Y10/00 ,  H01L27/115 ,  H01L29/7881

    摘要： Provided is a gate structure including a multi-tunneling layer and method of fabricating the same. Also provided is a nanodot semiconductor memory device including such gate structure and method of fabricating the same. The gate structure may include a first insulation layer, a second insulation layer, a charge storage layer including nanodots and formed on the second insulation layer, a third insulation layer formed on the charge storage layer, and a gate electrode layer formed on the third insulation layer. There may also be a nanodot semiconductor memory device including a semiconductor substrate, in which a first impurity region and a second impurity region may be formed, and including the gate structure formed on the semiconductor substrate which contacts the first and second impurity regions. The second insulation layer may be formed on the first insulation layer and may include a material whose energy level may be lower than an energy level of the conduction band of the first insulation layer and higher an energy level of the valence band of the first insulation layer.

    摘要翻译： 提供一种包括多隧道层的栅极结构及其制造方法。 还提供了包括这种栅极结构的纳米点半导体存储器件及其制造方法。 栅极结构可以包括第一绝缘层，第二绝缘层，包括纳米点并形成在第二绝缘层上的电荷存储层，形成在电荷存储层上的第三绝缘层，以及形成在第三绝缘层上的栅电极层 层。 还可以存在包括可以形成第一杂质区域和第二杂质区域的半导体衬底的纳米点半导体存储器件，并且包括形成在与第一和第二杂质区域接触的半导体衬底上的栅极结构。 第二绝缘层可以形成在第一绝缘层上，并且可以包括其能级可以低于第一绝缘层的导带的能级的材料，并且第一绝缘层的价带的能级越高 。

    Nonvolatile memory device and method for operating the same
    8.
    发明申请
    Nonvolatile memory device and method for operating the same 有权
    非易失性存储器件及其操作方法

    公开(公告)号：US20100172182A1

    公开(公告)日：2010-07-08

    申请号：US12654712

    申请日：2009-12-30

    申请人： Kwang-Soo Seol ,  Yoondong Park ,  Sukpil Kim

    发明人： Kwang-Soo Seol ,  Yoondong Park ,  Sukpil Kim

    IPC分类号： G11C16/04

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/3427 ,  G11C2213/71 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582

    摘要： Disclosed is a nonvolatile memory device which includes a plurality of cell array layers stacked on a semiconductor substrate. Each of the plurality of cell array layers includes a plurality of strings. Each of the plurality of strings has string and ground select transistors and a plurality of memory cells connected in series between the string and ground select transistors. A common source line is on each of the plurality of cell array layers. Each common source line is connected with first sides of the plurality of strings on a corresponding cell array layer. A plurality of bit lines is connected with second sides of the plurality of strings disposed on the cell array layers and arranged in the vertical direction to the semiconductor substrate. A plurality of word lines is connected with the plurality of memory cells.

    摘要翻译： 公开了一种非易失性存储器件，其包括堆叠在半导体衬底上的多个单元阵列层。 多个单元阵列层中的每一个包括多个串。 多个串中的每一个具有串和地选择晶体管以及串联连接在串和地选择晶体管之间的多个存储单元。 在多个单元阵列层中的每一个上都具有公共源极线。 每个公共源极线与相应的单元阵列层上的多个串的第一侧连接。 多个位线与布置在单元阵列层上的多个串的第二侧连接，并且在与半导体基板垂直的方向上布置。 多个字线与多个存储单元连接。

    Nonvolatile memory device and method for operating the same
    9.
    发明授权
    Nonvolatile memory device and method for operating the same 有权
    非易失性存储器件及其操作方法

    公开(公告)号：US08335109B2

    公开(公告)日：2012-12-18

    申请号：US12654712

    申请日：2009-12-30

    申请人： Kwang-Soo Seol ,  Yoondong Park ,  Sukpil Kim

    发明人： Kwang-Soo Seol ,  Yoondong Park ,  Sukpil Kim

    IPC分类号： G11C16/04

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/3427 ,  G11C2213/71 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582

    摘要： Disclosed is a nonvolatile memory device which includes a plurality of cell array layers stacked on a semiconductor substrate. Each of the plurality of cell array layers includes a plurality of strings. Each of the plurality of strings has string and ground select transistors and a plurality of memory cells connected in series between the string and ground select transistors. A common source line is on each of the plurality of cell array layers. Each common source line is connected with first sides of the plurality of strings on a corresponding cell array layer. A plurality of bit lines is connected with second sides of the plurality of strings disposed on the cell array layers and arranged in the vertical direction to the semiconductor substrate. A plurality of word lines is connected with the plurality of memory cells.

    摘要翻译： 公开了一种非易失性存储器件，其包括堆叠在半导体衬底上的多个单元阵列层。 多个单元阵列层中的每一个包括多个串。 多个串中的每一个具有串和地选择晶体管以及串联连接在串和地选择晶体管之间的多个存储单元。 在多个单元阵列层中的每一个上都具有公共源极线。 每个公共源极线与相应的单元阵列层上的多个串的第一侧连接。 多个位线与布置在单元阵列层上的多个串的第二侧连接，并且在与半导体基板垂直的方向上布置。 多个字线与多个存储单元连接。