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    High voltage GaN-based transistor structure
    3.
    发明授权
    High voltage GaN-based transistor structure 有权
    高电压GaN基晶体管结构

    公开(公告)号：US07026665B1

    公开(公告)日：2006-04-11

    申请号：US10689979

    申请日：2003-10-20

    申请人： Joseph Smart ,  Brook Hosse ,  Shawn Gibb ,  David Grider ,  Jeffrey Shealy

    发明人： Joseph Smart ,  Brook Hosse ,  Shawn Gibb ,  David Grider ,  Jeffrey Shealy

    IPC分类号： H01L31/072 ,  H01L31/109

    CPC分类号： H01L29/7787 ,  H01L29/2003

    摘要： The present invention relates to a high voltage and high power gallium nitride (GaN) transistor structure. In general, the GaN transistor structure includes a sub-buffer layer that serves to prevent injection of electrons into a substrate during high voltage operation, thereby improving performance of the GaN transistor structure during high voltage operation. Preferably, the sub-buffer layer is aluminum nitride, and the GaN transistor structure further includes a transitional layer, a GaN buffer layer, and an aluminum gallium nitride Schottky layer.

    摘要翻译： 本发明涉及高电压和高功率氮化镓（GaN）晶体管结构。 通常，GaN晶体管结构包括用于在高电压操作期间防止电子注入到衬底中的子缓冲层，从而在高电压操作期间改善GaN晶体管结构的性能。 优选地，子缓冲层是氮化铝，并且GaN晶体管结构还包括过渡层，GaN缓冲层和氮化镓铝肖特基层。

    Single step, high temperature nucleation process for a lattice mismatched substrate
    4.
    发明申请
    Single step, high temperature nucleation process for a lattice mismatched substrate 有权
    单步，高温成核过程的晶格失配衬底

    公开(公告)号：US20060199364A1

    公开(公告)日：2006-09-07

    申请号：US11069040

    申请日：2005-03-02

    申请人： James Shealy ,  Joseph Smart

    发明人： James Shealy ,  Joseph Smart

    IPC分类号： H01L21/44

    CPC分类号： H01L21/02562 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02557 ,  H01L21/0262 ,  H01L21/02658

    摘要： A single step process for nucleation and subsequent epitaxial growth on a lattice mismatched substrate is achieved by pre-treating the substrate surface with at least one group III reactant or at least one group II reactant prior to the introduction of a group V reactant or a group VI reactant. The group III reactant or the group II reactant is introduced into a growth chamber at an elevated growth temperature to wet a substrate surface prior to any actual crystal growth. Once the pre-treatment of the surface is complete, a group V reactant or a group VI reactant is introduced to the growth chamber to commence the deposition of a nucleation layer. A buffer layer is then grown on the nucleation layer providing a surface upon which the epitaxial layer is grown preferably without changing the temperature within the chamber.

    摘要翻译： 通过在引入V族反应物或基团之前用至少一种III族反应物或至少一种II族反应物预处理底物表面来实现晶格失配衬底上的成核和随后的外延生长的单步过程 VI反应物。 将III族反应物或II族反应物在升高的生长温度下引入生长室中，以在任何实际的晶体生长之前润湿基底表面。 一旦表面的预处理完成，将V族反应物或VI族反应物引入生长室，开始沉积成核层。 然后在成核层上生长缓冲层，提供外延层生长的表面，而不改变室内的温度。

    Surface passivation of GaN devices in epitaxial growth chamber
    5.
    发明授权
    Surface passivation of GaN devices in epitaxial growth chamber 有权
    外延生长室中GaN器件的表面钝化

    公开(公告)号：US07408182B1

    公开(公告)日：2008-08-05

    申请号：US11397279

    申请日：2006-04-04

    申请人： Joseph Smart ,  David Grider ,  Shawn Gibb ,  Brook Hosse ,  Jeffrey Shealy

    发明人： Joseph Smart ,  David Grider ,  Shawn Gibb ,  Brook Hosse ,  Jeffrey Shealy

    IPC分类号： H01L29/06 ,  H01L29/26

    CPC分类号： H01L29/66462 ,  H01L21/3185 ,  H01L29/2003 ,  H01L29/7787

    摘要： The present invention relates to passivation of a gallium nitride (GaN) structure before the GaN structure is removed from an epitaxial growth chamber. The GaN structure includes one or more structural epitaxial layers deposited on a substrate, and the passivation layer deposited on the structural epitaxial layers. In general, the passivation layer is a dielectric material deposited on the GaN structure that serves to passivate surface traps on the surface of the structural epitaxial layers. Preferably, the passivation layer is a dense, thermally deposited silicon nitride passivation layer.

    摘要翻译： 本发明涉及在从外延生长室移除GaN结构之前氮化镓（GaN）结构的钝化。 GaN结构包括沉积在衬底上的一个或多个结构外延层，以及沉积在结构外延层上的钝化层。 通常，钝化层是沉积在GaN结构上的电介质材料，其用于钝化结构外延层的表面上的表面陷阱。 优选地，钝化层是致密的，热沉积的氮化硅钝化层。

    Epitaxy/substrate release layer
    6.
    发明授权
    Epitaxy/substrate release layer 有权
    外延/底物释放层

    公开(公告)号：US07033961B1

    公开(公告)日：2006-04-25

    申请号：US10620205

    申请日：2003-07-15

    申请人： Joseph Smart ,  Brook Hosse ,  Shawn Gibb ,  David Grider ,  Jeffrey B. Shealy

    发明人： Joseph Smart ,  Brook Hosse ,  Shawn Gibb ,  David Grider ,  Jeffrey B. Shealy

    IPC分类号： H01L21/26

    CPC分类号： H01L29/7787 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/66462

    摘要： The present invention relates to an epitaxial structure having one or more structural epitaxial layers, including a gallium nitride (GaN) layer, which is deposited on a substrate, and a method of growing the epitaxial structure, wherein the structural epitaxial layers can be separated from the substrate. In general, a sacrificial epitaxial layer is deposited on the substrate between the substrate and the structural epitaxial layers, and the structural epitaxial layers are deposited on the sacrificial layer. After growth, the structural epitaxial layers are separated from the substrate by oxidizing the sacrificial layer. The structural epitaxial layers include a nucleation layer deposited on the sacrificial layer and a gallium nitride layer deposited on the nucleation layer. Optionally, the oxidation of the sacrificial layer may also oxidize the nucleation layer.

    摘要翻译： 本发明涉及具有一个或多个结构外延层的外延结构，其包括沉积在衬底上的氮化镓（GaN）层，以及生长外延结构的方法，其中结构外延层可以与 底物。 通常，在基板和结构外延层之间的衬底上沉积牺牲性外延层，并且将结构外延层沉积在牺牲层上。 生长后，通过氧化牺牲层将结构外延层与衬底分离。 结构外延层包括沉积在牺牲层上的成核层和沉积在成核层上的氮化镓层。 任选地，牺牲层的氧化也可以氧化成核层。

    High voltage GaN-based transistor structure
    7.
    发明授权
    High voltage GaN-based transistor structure 有权
    高电压GaN基晶体管结构

    公开(公告)号：US07968391B1

    公开(公告)日：2011-06-28

    申请号：US11937207

    申请日：2007-11-08

    申请人： Joseph Smart ,  Brook Hosse ,  Shawn Gibb ,  David Grider ,  Jeffrey B. Shealy

    发明人： Joseph Smart ,  Brook Hosse ,  Shawn Gibb ,  David Grider ,  Jeffrey B. Shealy

    IPC分类号： H01L21/338

    CPC分类号： H01L29/7787 ,  H01L29/2003

    摘要： A high voltage and high power gallium nitride (GaN) transistor structure is disclosed. A plurality of structural epitaxial layers including a GaN buffer layer is deposited on a substrate. A GaN termination layer is deposited on the plurality of structural epitaxial layers. The GaN termination layer is adapted to protect the plurality of structural epitaxial layers from surface reactions. The GaN termination layer is sufficiently thin to allow electrons to tunnel through the GaN termination layer. Electrical contacts are deposited on the GaN termination layer, thereby forming a high electron mobility transistor.

    摘要翻译： 公开了高电压和高功率氮化镓（GaN）晶体管结构。 在衬底上沉积包括GaN缓冲层的多个结构外延层。 在多个结构外延层上沉积GaN终止层。 GaN端接层适于保护多个结构外延层免受表面反应。 GaN终端层足够薄以允许电子穿过GaN终端层。 电触点沉积在GaN终端层上，从而形成高电子迁移率晶体管。

    High voltage GaN-based transistor structure
    8.
    发明授权
    High voltage GaN-based transistor structure 有权
    高电压GaN基晶体管结构

    公开(公告)号：US07459356B1

    公开(公告)日：2008-12-02

    申请号：US11360734

    申请日：2006-02-23

    申请人： Joseph Smart ,  Brook Hosse ,  Shawn Gibb ,  David Grider ,  Jeffrey Shealy

    发明人： Joseph Smart ,  Brook Hosse ,  Shawn Gibb ,  David Grider ,  Jeffrey Shealy

    IPC分类号： H01L21/338

    CPC分类号： H01L29/7787 ,  H01L29/2003

    摘要： The present invention relates to a high voltage and high power gallium nitride (GaN) transistor structure. In general, the GaN transistor structure includes a sub-buffer layer that serves to prevent injection of electrons into a substrate during high voltage operation, thereby improving performance of the GaN transistor structure during high voltage operation. Preferably, the sub-buffer layer is aluminum nitride, and the GaN transistor structure further includes a transitional layer, a GaN buffer layer, and an aluminum gallium nitride Schottky layer.

    摘要翻译： 本发明涉及高电压和高功率氮化镓（GaN）晶体管结构。 通常，GaN晶体管结构包括用于在高电压操作期间防止电子注入到衬底中的子缓冲层，从而在高电压操作期间改善GaN晶体管结构的性能。 优选地，子缓冲层是氮化铝，并且GaN晶体管结构还包括过渡层，GaN缓冲层和氮化镓铝肖特基层。

    Surface passivation of GaN devices in epitaxial growth chamber
    9.
    发明授权
    Surface passivation of GaN devices in epitaxial growth chamber 有权
    外延生长室中GaN器件的表面钝化

    公开(公告)号：US07052942B1

    公开(公告)日：2006-05-30

    申请号：US10689980

    申请日：2003-10-20

    申请人： Joseph Smart ,  David Grider ,  Shawn Gibb ,  Brook Hosse ,  Jeffrey Shealy

    发明人： Joseph Smart ,  David Grider ,  Shawn Gibb ,  Brook Hosse ,  Jeffrey Shealy

    IPC分类号： H01L21/84 ,  H01L21/338 ,  H01L31/0328

    CPC分类号： H01L29/66462 ,  H01L21/3185 ,  H01L29/2003 ,  H01L29/7787

    摘要： The present invention relates to passivation of a gallium nitride (GaN) structure before the GaN structure is removed from an epitaxial growth chamber. The GaN structure includes one or more structural epitaxial layers deposited on a substrate, and the passivation layer deposited on the structural epitaxial layers. In general, the passivation layer is a dielectric material deposited on the GaN structure that serves to passivate surface traps on the surface of the structural epitaxial layers. Preferably, the passivation layer is a dense, thermally deposited silicon nitride passivation layer.

    摘要翻译： 本发明涉及在从外延生长室移除GaN结构之前氮化镓（GaN）结构的钝化。 GaN结构包括沉积在衬底上的一个或多个结构外延层，以及沉积在结构外延层上的钝化层。 通常，钝化层是沉积在GaN结构上的电介质材料，其用于钝化结构外延层的表面上的表面陷阱。 优选地，钝化层是致密的，热沉积的氮化硅钝化层。