公开(公告)号：US20170084586A1

公开(公告)日：2017-03-23

申请号：US15162538

申请日：2016-05-23

Applicant: LEXTAR ELECTRONICS CORPORATION

Inventor： Yi-Jyun CHEN ,  Chih-Hao LIN

IPC: H01L25/075 ,  H01L33/50 ,  H01L33/60 ,  H01L33/08 ,  H01L33/62

CPC classification number: H01L25/0753 ,  H01L25/0756 ,  H01L27/15 ,  H01L33/08 ,  H01L33/502 ,  H01L33/60 ,  H01L33/62

Abstract: An LED chip package includes a substrate having a metal terminal (gold finger structure). A LED chip set is composed of a plurality of LED chips formed in one piece, and has a plurality of light-emitting areas which are separated from each other. The LED chip set is disposed on the substrate and electrically connected to the metal terminal.

公开(公告)号：US20190131342A1

公开(公告)日：2019-05-02

申请号：US16171334

申请日：2018-10-25

Applicant: Lextar Electronics Corporation

Inventor： Yi-Jyun CHEN ,  Li-Cheng YANG ,  Yu-Chun LEE ,  Shiou-Yi KUO ,  Chih-Hao LIN

IPC: H01L27/15 ,  H01L33/50 ,  H01L33/38 ,  H01L33/08 ,  H01L33/52 ,  H01L25/075

Abstract: A pixel structure includes a light emitting diode chip and a light blocking structure. The light emitting diode chip includes a P-type semiconductor layer, an active layer, an N-type semiconductor layer, a first electrode, and K second electrodes. The active layer is located on the P-type semiconductor layer. The N-type semiconductor layer is located on the active layer. The N-type semiconductor layer has a first top surface that is distant from the active layer. The first electrode is electrically connected to the P-type semiconductor layer. The light blocking structure is located in the light emitting diode chip and defines K sub-pixel regions. The active layer and the N-type semiconductor layer are divided into K sub-portions respectively corresponding to the K sub-pixel regions by the light blocking structure. The K sub-pixel regions share the P-type semiconductor layer.

公开(公告)号：US20150097207A1

公开(公告)日：2015-04-09

申请号：US14271390

申请日：2014-05-06

Applicant: LEXTAR ELECTRONICS CORPORATION

Inventor： Yi-Jyun CHEN

IPC: H01L23/38

CPC classification number: H01L23/38 ,  H01L35/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor chip structure including a semiconductor chip having a pair of electrodes is disclosed. The electrodes have different conductivity types for electrical connection, respectively. A thermoelectric cooling material layer is disposed within each of the pair of electrodes, respectively.

Abstract translation: 公开了一种包括具有一对电极的半导体芯片的半导体芯片结构。 电极分别具有不同的导电类型用于电连接。 热电冷却材料层分别设置在每对电极中。

公开(公告)号：US20160365493A1

公开(公告)日：2016-12-15

申请号：US15054065

申请日：2016-02-25

Applicant: LEXTAR ELECTRONICS CORPORATION

Inventor： Hsin-Lun SU ,  Chih-Hao LIN ,  Fang-Chang HSUEH ,  Tzong-Liang TSAI ,  Yi-Jyun CHEN

IPC: H01L33/56

CPC classification number: H01L33/486 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A light-emitting diode device includes a shell with a recess, wherein the shell does not contain metal oxide. A plurality of lead frames extends from the bottom of the recess to the outside of the shell. At least an UV light-emitting diode (LED) chip is disposed on the bottom of the recess and is electrically connected to the lead frames, wherein the UV LED chip has a wavelength range of 200 nm-400 nm. In addition, an encapsulation adhesive fills the recess to cover the UV LED chip.

Abstract translation: 发光二极管装置包括具有凹部的外壳，其中外壳不含有金属氧化物。 多个引线框架从凹部的底部延伸到外壳的外部。 至少一个UV发光二极管（LED）芯片设置在凹槽的底部并且电连接到引线框架，其中UV LED芯片具有200nm-400nm的波长范围。 此外，封装粘合剂填充凹部以覆盖UV LED芯片。

公开(公告)号：US20150108650A1

公开(公告)日：2015-04-23

申请号：US14272468

申请日：2014-05-07

Applicant: LEXTAR ELECTRONICS CORPORATION

Inventor： Yi-Jyun CHEN

IPC: H01L23/00

CPC classification number: H01L24/32 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/2745 ,  H01L2224/276 ,  H01L2224/2783 ,  H01L2224/29005 ,  H01L2224/29012 ,  H01L2224/29013 ,  H01L2224/29016 ,  H01L2224/29023 ,  H01L2224/29076 ,  H01L2224/2908 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32054 ,  H01L2224/32056 ,  H01L2224/32113 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32502 ,  H01L2224/32506 ,  H01L2224/83805 ,  H01L2224/83815 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

Abstract: The present invention provides a eutectic solder structure for a chip including a substrate and a solder structure on the substrate. The solder structure includes an alternate lamination of a plurality of first metal layers and a plurality of second metal layers, wherein each second metal layer has a continuous region and a plurality of openings and the melting point of the plurality of second metal layers is higher than that of the plurality of first metal layers. The eutectic solder structure for a chip also includes a chip on the solder structure, wherein the chip is bonded to the substrate by a eutectic reaction of the solder structure.

Abstract translation: 本发明提供了一种用于芯片的共晶焊料结构，其包括在基板上的基板和焊料结构。 焊料结构包括多个第一金属层和多个第二金属层的交替叠层，其中每个第二金属层具有连续区域和多个开口，并且多个第二金属层的熔点高于 多个第一金属层中的第一金属层。 用于芯片的共晶焊料结构还包括焊料结构上的芯片，其中芯片通过焊料结构的共晶反应结合到衬底。