公开(公告)号：US08569173B2

公开(公告)日：2013-10-29

申请号：US13314270

申请日：2011-12-08

申请人： Liang Li ,  Huang Liu ,  Alex See ,  Soh Yun Siah ,  Xue Song Rao ,  Peng Zhou

发明人： Liang Li ,  Huang Liu ,  Alex See ,  Soh Yun Siah ,  Xue Song Rao ,  Peng Zhou

IPC分类号： H01L21/302

CPC分类号： H01L27/11534 ,  H01L21/28273

摘要： Disclosed herein are various methods of protecting elevated polysilicon structures during etching processes. In one example, the method includes forming a layer stack above a semiconducting substrate for a memory device, forming a protective mask layer above the layer stack of the memory device and performing at least one etching process to define a gate electrode for a transistor while the protective mask is in position above the layer stack for the memory device.

摘要翻译： 本文公开了在蚀刻工艺期间保护升高的多晶硅结构的各种方法。 在一个示例中，该方法包括在用于存储器件的半导体衬底之上形成层堆叠，在存储器件的层堆叠之上形成保护掩模层，并执行至少一个蚀刻工艺以限定晶体管的栅电极，而 保护罩位于存储器件的层堆叠之上。

公开(公告)号：US20130149851A1

公开(公告)日：2013-06-13

申请号：US13314270

申请日：2011-12-08

申请人： Liang Li ,  Huang Liu ,  Alex See ,  Soh Yun Siah ,  Xue Song Rao ,  Peng Zhou

发明人： Liang Li ,  Huang Liu ,  Alex See ,  Soh Yun Siah ,  Xue Song Rao ,  Peng Zhou

IPC分类号： H01L21/28

CPC分类号： H01L27/11534 ,  H01L21/28273

摘要： Disclosed herein are various methods of protecting elevated polysilicon structures during etching processes. In one example, the method includes forming a layer stack above a semiconducting substrate for a memory device, forming a protective mask layer above the layer stack of the memory device and performing at least one etching process to define a gate electrode for a transistor while the protective mask is in position above the layer stack for the memory device.

摘要翻译： 本文公开了在蚀刻工艺期间保护升高的多晶硅结构的各种方法。 在一个示例中，该方法包括在用于存储器件的半导体衬底之上形成层堆叠，在存储器件的层堆叠之上形成保护掩模层，并执行至少一个蚀刻工艺以限定晶体管的栅电极，而 保护罩位于存储器件的层堆叠之上。

公开(公告)号：US08852968B2

公开(公告)日：2014-10-07

申请号：US13768870

申请日：2013-02-15

申请人： Liang Li ,  Zheng Zou ,  Huang Liu ,  Alex See

发明人： Liang Li ,  Zheng Zou ,  Huang Liu ,  Alex See

IPC分类号： H01L21/66

CPC分类号： H01L22/12 ,  G01B2210/56

摘要： Methods of deducing oxide thickness using calculated and measured scattering spectra are provided. Embodiments include depositing an oxide over a semiconductor wafer, reducing the oxide from a portion of the semiconductor wafer, and deducing a thickness of oxide remaining at a location within the portion using scatterometric metrology. Embodiments further include deducing the thickness by: calculating scattering spectra for a plurality of oxide thicknesses, producing calculated scattering spectra, monitoring scattering spectra at the location within the portion of the semiconductor wafer, comparing the monitored scattering spectra at the location to the calculated scattering spectra, determining a closest matching calculated scattering spectra to the monitored scattering spectra at the location, and obtaining an oxide thickness corresponding to the closest matching calculated scattering spectra.

摘要翻译： 提供了使用计算和测量的散射光谱推导氧化物厚度的方法。 实施例包括在半导体晶片上沉积氧化物，从半导体晶片的一部分还原氧化物，并使用散射测量法推算残留在该部分内部的氧化物的厚度。 实施例还包括通过以下方式推导厚度：计算多个氧化物厚度的散射光谱，产生计算的散射光谱，监测半导体晶片部分内的位置处的散射光谱，将该位置处的所监视的散射光谱与计算出的散射光谱进行比较 确定与所述位置处的所监视的散射光谱最接近的匹配计算的散射光谱，以及获得对应于最接近的匹配计算的散射光谱的氧化物厚度。

公开(公告)号：US20140117545A1

公开(公告)日：2014-05-01

申请号：US13661882

申请日：2012-10-26

申请人： Huang LIU ,  Xuesong Rao ,  Zheng Zou ,  Alex See ,  Lup San Leong ,  Liang Li ,  Chim Seng Seet

发明人： Huang LIU ,  Xuesong Rao ,  Zheng Zou ,  Alex See ,  Lup San Leong ,  Liang Li ,  Chim Seng Seet

IPC分类号： H01L21/768 ,  H01L23/48

CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

摘要： A copper layer is formed without copper hillocks. Embodiments includes providing a copper layer above a substrate, planarizing the copper layer, performing hydrogen (H2) plasma treatment on the copper layer in a first chamber, and forming a barrier layer over the copper layer in a second chamber, different from the first chamber.

摘要翻译： 形成铜层，没有铜质的小丘。 实施例包括在基板上设置铜层，对铜层进行平坦化，对第一室中的铜层进行氢（H2）等离子体处理，以及在不同于第一室的第二室中的铜层上形成阻挡层 。

公开(公告)号：US08492236B1

公开(公告)日：2013-07-23

申请号：US13348766

申请日：2012-01-12

申请人： Xuesong Rao ,  Chim Seng Seet ,  Hai Cong ,  Zheng Zou ,  Alex See ,  Yun Ling Tan ,  Wen Zhan Zhou ,  Lup San Leong ,  Huang Liu

发明人： Xuesong Rao ,  Chim Seng Seet ,  Hai Cong ,  Zheng Zou ,  Alex See ,  Yun Ling Tan ,  Wen Zhan Zhou ,  Lup San Leong ,  Huang Liu

IPC分类号： H01L21/336

CPC分类号： H01L29/6656 ,  H01L29/78

摘要： Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a step-like or tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode, etching the spacer material to form a first spacer on each side of the gate electrode, and pulling back the first spacers to form second spacers which have a step-like profile. Embodiments further include depositing a second spacer material over the gate electrode and the second spacers, and etching the second spacer material to form a third spacer on each second spacer, the second and third spacers forming an outwardly tapered composite spacer.

摘要翻译： 通过形成具有阶梯状或锥形轮廓的栅极间隔物来增强层间电介质间隙填充工艺。 实施例包括在衬底上形成栅电极，在栅电极上沉积间隔物材料，蚀刻间隔物材料以在栅电极的每一侧上形成第一间隔物，并拉回第一间隔物以形成第二间隔物， 像个人资料 实施例还包括在栅极电极和第二间隔物上沉积第二间隔物材料，并蚀刻第二间隔物材料以在每个第二间隔物上形成第三间隔物，第二和第三间隔物形成向外锥形的复合间隔物。

公开(公告)号：US20130181259A1

公开(公告)日：2013-07-18

申请号：US13348766

申请日：2012-01-12

申请人： Xuesong Rao ,  Chim Seng Seet ,  Hai Cong ,  Zheng Zou ,  Alex See ,  Yun Ling Tan ,  Wen Zhan Zhou ,  Lup San Leong ,  Huang Liu

发明人： Xuesong Rao ,  Chim Seng Seet ,  Hai Cong ,  Zheng Zou ,  Alex See ,  Yun Ling Tan ,  Wen Zhan Zhou ,  Lup San Leong ,  Huang Liu

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/6656 ,  H01L29/78

摘要： Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a step-like or tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode, etching the spacer material to form a first spacer on each side of the gate electrode, and pulling back the first spacers to form second spacers which have a step-like profile. Embodiments further include depositing a second spacer material over the gate electrode and the second spacers, and etching the second spacer material to form a third spacer on each second spacer, the second and third spacers forming an outwardly tapered composite spacer.

摘要翻译： 通过形成具有阶梯状或锥形轮廓的栅极间隔物来增强层间电介质间隙填充工艺。 实施例包括在衬底上形成栅电极，在栅电极上沉积间隔物材料，蚀刻间隔物材料以在栅电极的每一侧上形成第一间隔物，并拉回第一间隔物以形成第二间隔物， 像个人资料 实施例还包括在栅极电极和第二间隔物上沉积第二间隔物材料，并蚀刻第二间隔物材料以在每个第二间隔物上形成第三间隔物，第二和第三间隔物形成向外锥形的复合间隔物。

公开(公告)号：US20070293039A1

公开(公告)日：2007-12-20

申请号：US11454397

申请日：2006-06-16

申请人： Xiaomei Bu ,  Alex See ,  Fan Zhang ,  Jane Hui ,  Tae Jong Lee ,  Liang Choo Hsia

发明人： Xiaomei Bu ,  Alex See ,  Fan Zhang ,  Jane Hui ,  Tae Jong Lee ,  Liang Choo Hsia

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/288 ,  H01L21/2885 ,  H01L21/76873 ,  H01L21/76877

摘要： A method of filling gaps in dielectric layers is disclosed. A wafer is provided having a dielectric layer containing gaps to be filled with copper, some of the gaps, denoted deeper gaps, having aspect ratios so large that filling these gaps with copper using ECP could result in pinhole like voids. A blanket conformal metal barrier layer is formed and the wafer is then submerged in a solution to electroless plate a blanket conformal copper seed layer. A partial filling of deeper gaps with copper reduces the effective aspect ratios of the deeper gaps to the extent that ECP could be used to complete the copper filling of the gaps without forming pinhole like voids. ECP is then used to complete the copper filling of the gaps. The wafer is annealed and CMP performed to planarize the surface, giving rise to a structure in which the gaps are filled with copper and are separated by the dielectric layer.

摘要翻译： 公开了一种在电介质层中填充间隙的方法。 提供具有包含要填充铜的间隙的电介质层的晶片，其中一些间隙表示为更深的间隙，其纵横比大到使用ECP填充这些间隙的铜可导致针孔状空隙。 形成覆盖的共形金属阻挡层，然后将晶片浸没在无电镀平板上的覆盖层保形铜种子层的溶液中。 用铜部分填充更深的间隙可以减少较深间隙的有效纵横比，使得ECP可以用于完成间隙的铜填充而不形成针孔如空隙的程度。 然后使用ECP来完成间隙的铜填充。 对晶片进行退火并进行CMP以平坦化表面，产生其中间隙被铜填充并由介电层分离的结构。

公开(公告)号：US20060286797A1

公开(公告)日：2006-12-21

申请号：US11153747

申请日：2005-06-15

申请人： Fan Zhang ,  Kho Liep ,  Alex See ,  Cheng-Cheh Tou ,  Xiaomei Bu ,  Tae Lee ,  Liang Hsia

发明人： Fan Zhang ,  Kho Liep ,  Alex See ,  Cheng-Cheh Tou ,  Xiaomei Bu ,  Tae Lee ,  Liang Hsia

IPC分类号： H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/76859 ,  H01L21/76856 ,  H01L21/76864

摘要： Example embodiments of a structure and method for forming a copper interconnect having a doped region near a top surface. The doped region has implanted alloying elements that block grain boundaries and reduce stress and electro migration. In a first example embodiment, the barrier layer is left over the inter metal dielectric layer during the alloying element implant. The barrier layer is later removed with a planarization process. In a second example embodiment the barrier layer is removed before the alloying element implant and a hard mask blocks the alloying element from being implanted in the inter metal dielectric layer.

摘要翻译： 用于形成具有在顶表面附近的掺杂区域的铜互连的结构和方法的示例实施例。 掺杂区域已经植入了阻挡晶界并减少应力和电迁移的合金元素。 在第一示例性实施例中，在合金元素植入期间，阻挡层留在金属间介电层上。 稍后通过平坦化处理去除阻挡层。 在第二示例性实施例中，在合金元素注入之前去除阻挡层，并且硬掩模阻止合金元素被注入在金属间介电层中。

公开(公告)号：US20060040491A1

公开(公告)日：2006-02-23

申请号：US10923123

申请日：2004-08-21

申请人： Yeow Lim ,  Alex See ,  Tae Lee ,  David Vigar ,  Liang Hsia ,  Kin Pey

发明人： Yeow Lim ,  Alex See ,  Tae Lee ,  David Vigar ,  Liang Hsia ,  Kin Pey

IPC分类号： H01L21/4763

CPC分类号： H01L23/528 ,  H01L21/0276 ,  H01L21/288 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that the first slot relieves stress on the wide line and the via plug. The via plug can contact the wide line from above or below. Another example embodiment is a dual damascene interconnect structure comprising: an dual damascene shaped interconnect comprising a via plug, a first slot and a wide line. The wide line has the first slot. The first slot is spaced a first distance from the via plug so that the first slot relieves stress on the wide line and the via plug.

摘要翻译： 用于宽线槽以减少压力的方法和结构。 一种示例性实施例的方法和结构是一种互连结构，包括：包括宽线的互连。 宽线有第一个插槽。 第一槽与通孔塞隔开第一距离，使得第一槽减轻宽线和通孔塞上的应力。 通孔插头可以从上方或下方接触宽线。 另一个示例性实施例是双镶嵌互连结构，包括：双镶嵌形互连件，其包括通孔塞，第一槽和宽线。 宽线有第一个插槽。 第一槽与通孔塞隔开第一距离，使得第一槽减轻宽线和通孔塞上的应力。

公开(公告)号：US20050156269A1

公开(公告)日：2005-07-21

申请号：US11081908

申请日：2005-03-15

申请人： Pooi Lee ,  Kin Pey ,  Alex See ,  Lap Chan

发明人： Pooi Lee ,  Kin Pey ,  Alex See ,  Lap Chan

IPC分类号： H01L21/265 ,  H01L21/285 ,  H01L21/336 ,  H01L29/49 ,  H01L27/095

CPC分类号： H01L29/665 ,  H01L21/26506 ,  H01L21/28518 ,  H01L29/4933

摘要： A method and apparatus for performing nickel salicidation is disclosed. The nickel salicide process typically includes: forming a processed substrate including partially fabricated integrated circuit components and a silicon substrate; incorporating nitrogen into the processed substrate; depositing nickel onto the processed substrate; annealing the processed substrate so as to form nickel mono-silicide; removing the unreacted nickel; and performing a series procedures to complete integrated circuit fabrication. This nickel salicide process increases the annealing temperature range for which a continuous, thin nickel mono-silicide layer can be formed on silicon by salicidation. It also delays the onset of agglomeration of nickel mono-silicide thin-films to a higher annealing temperature. Moreover, this nickel salicide process delays the transformation from nickel mono-silicide to higher resistivity nickel di-silicide, to higher annealing temperature. It also reduces nickel enhanced poly-silicon grain growth to prevent layer inversion. Some embodiments of this nickel salicide process may be used in an otherwise standard salicide process, to form integrated circuit devices with low resistivity transistor gate electrodes and source/drain contacts.