公开(公告)号：US12237259B2

公开(公告)日：2025-02-25

申请号：US17443531

申请日：2021-07-27

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  Harsh Narendrakumar Jain ,  Naveen Kaushik ,  Adam L. Olson ,  Richard J. Hill ,  Lars P. Heineck

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H10B41/35 ,  H10B43/35

Abstract: An electronic device comprising multilevel bitlines comprising first bitlines and second bitlines. The first bitlines and the second bitlines are positioned at different levels. Pillar contacts are electrically connected to the first bitlines and to the second bitlines. Level 1 contacts are electrically connected to the first bitlines and level 2 contacts are electrically connected to the second bitlines. A liner is between the first bitlines and the level 2 contacts. Each bitline of the first bitlines is electrically connected to a single pillar contact in a subblock adjacent to the level 1 contacts and each bitline of the second bitlines is electrically connected to a single pillar contact adjacent to the level 2 contacts. Methods of forming an electronic device and related systems are also disclosed.

公开(公告)号：US20230033803A1

公开(公告)日：2023-02-02

申请号：US17443531

申请日：2021-07-27

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  Harsh Narendrakumar Jain ,  Naveen Kaushik ,  Adam L. Olson ,  Richard J. Hill ,  Lars P. Heineck

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: An electronic device comprising multilevel bitlines comprising first bitlines and second bitlines. The first bitlines and the second bitlines are positioned at different levels. Pillar contacts are electrically connected to the first bitlines and to the second bitlines. Level 1 contacts are electrically connected to the first bitlines and level 2 contacts are electrically connected to the second bitlines. A liner is between the first bitlines and the level 2 contacts. Each bitline of the first bitlines is electrically connected to a single pillar contact in a subblock adjacent to the level 1 contacts and each bitline of the second bitlines is electrically connected to a single pillar contact adjacent to the level 2 contacts. Methods of forming an electronic device and related systems are also disclosed.

公开(公告)号：US20230032177A1

公开(公告)日：2023-02-02

申请号：US17443521

申请日：2021-07-27

Applicant: Micron Technology, Inc.

Inventor： Harsh Narendrakumar Jain ,  Adam L. Olson ,  Yoshiaki Fukuzumi ,  Naveen Kaushik ,  Richard J. Hill ,  Lars P. Heineck

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/02 ,  H01L23/00

Abstract: An electronic device comprising multilevel bitlines, pillar contacts, level 1 contacts, and level 2 contacts. The multilevel bitlines comprise first bitlines and second bitlines, with the first bitlines and second bitlines positioned at different levels. The pillar contacts are electrically connected to the first bitlines and to the second bitlines, the level 1 contacts are electrically connected to the first bitlines, and the level 2 contacts are electrically connected to the second bitlines. Each bitline of the first bitlines is electrically connected to a single pillar contact adjacent to the level 1 contacts and each bitline of the second bitlines is electrically connected to a single pillar contact adjacent to the level 2 contacts. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

公开(公告)号：US20220189827A1

公开(公告)日：2022-06-16

申请号：US17652346

申请日：2022-02-24

Applicant: Micron Technology, Inc.

Inventor： Bo Zhao ,  Nancy M. Lomeli ,  Lifang Xu ,  Adam L. Olson

IPC: H01L21/8229 ,  H01L21/768 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11578

Abstract: A microelectronic device comprises a microelectronic device structure having a memory array region and a staircase region. The microelectronic device structure comprises a stack structure having tiers each comprising a conductive structure and an insulative structure; staircase structures confined within the staircase region and having steps comprising edges of the tiers of the stack structure within the deck and the additional deck; and semiconductive pillar structures confined within the memory array region and extending through the stack structures. The stack structure comprises a deck comprising a group of the tiers; an additional deck overlying the deck and comprising an additional group of the tiers; and an interdeck section between the deck and the additional deck and comprising a dielectric structure confined within the memory array region, and another group of the tiers within vertical boundaries of the dielectric structure and confined within the staircase region.

公开(公告)号：US20200211981A1

公开(公告)日：2020-07-02

申请号：US16235665

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Rohit Kothari ,  Adam L. Olson ,  John D. Hopkins ,  Jeslin J. Wu

IPC: H01L23/00 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/762

Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.

公开(公告)号：US20180366406A1

公开(公告)日：2018-12-20

申请号：US16042255

申请日：2018-07-23

Applicant: Micron Technology, Inc.

Inventor： Adam L. Olson ,  Kaveri Jain ,  Lijing Gou ,  William R. Brown ,  Ho Seop Eom ,  Xue (Gloria) Chen ,  Anton J. deVilliers

IPC: H01L23/528 ,  H01L21/467 ,  H01L23/52 ,  H01L21/768 ,  H01L21/027 ,  H01L21/308 ,  H01L21/02

CPC classification number: H01L23/528 ,  H01L21/0226 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/441 ,  H01L21/467 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/52 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor structure comprises forming pools of acidic or basic material in a substrate structure. A resist is formed over the pools of acidic or basic material and the substrate structure. The acidic or basic material is diffused from the pools into portions of the resist proximal to the pools more than into portions of the resist distal to the pools. Then, the resist is exposed to a developer to remove a greater amount of the resist portions proximal to the pools compared to the resist portions distal to the pools to form openings in the resist. The openings have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure. The method may further comprise forming features in the openings of the resist. The features have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure.

公开(公告)号：US20170062337A1

公开(公告)日：2017-03-02

申请号：US14837978

申请日：2015-08-27

Applicant: Micron Technology, Inc.

Inventor： Matthew Park ,  Adam L. Olson ,  Jixin Yu

IPC: H01L23/528 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3213 ,  H01L27/115 ,  H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76804 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/7685 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/53295 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11582

Abstract: A method of forming a semiconductor device assembly comprises forming tiers comprising conductive structures and insulating structures in a stacked arrangement over a substrate. Portions of the tiers are selectively removed to form a stair step structure comprising a selected number of steps exhibiting different widths corresponding to variances in projected error associated with forming the steps. Contact structures are formed on the steps of the stair step structure. Semiconductor device structures and semiconductor devices are also described.

Abstract translation: 形成半导体器件组件的方法包括在衬底上层叠布置形成包括导电结构和绝缘结构的层。 选择性地移除层的部分以形成阶梯结构，其包括对应于与形成步骤相关联的投影误差的方差显示不同宽度的选定数量的步骤。 在阶梯结构的台阶上形成接触结构。 还描述了半导体器件结构和半导体器件。

公开(公告)号：US20250157950A1

公开(公告)日：2025-05-15

申请号：US19025955

申请日：2025-01-16

Applicant: Micron Technology, Inc.

Inventor： Rohit Kothari ,  Adam L. Olson ,  John D. Hopkins ,  Jeslin J. Wu

IPC: H01L23/00 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762

Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.

公开(公告)号：US11563027B2

公开(公告)日：2023-01-24

申请号：US17016002

申请日：2020-09-09

Applicant: Micron Technology, Inc.

Inventor： Md Zakir Ullah ,  Xiaosong Zhang ,  Adam L. Olson ,  Mohammad Moydul Islam ,  Tien Minh Quan Tran ,  Chao Zhu ,  Zhigang Yang ,  Merri L. Carlson ,  Hui Chin Chong ,  David A. Kewley ,  Kok Siak Tang

IPC: H01L27/11582 ,  H01L27/11556

Abstract: Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A lower array of pillars extends through the stack structure of the lower deck, and an upper array of pillars extends through the stack structure of the upper deck. Along an interface between the lower deck and the upper deck, the pillars of the lower array align with the pillars of the upper array. At least at elevations comprising bases of the pillars, a pillar density of the pillars of the lower array differs from a pillar density of the pillars of the upper array, “pillar density” being a number of pillars per unit of horizontal area of the respective array. Related methods and electronic systems are also disclosed.

公开(公告)号：US20210167079A1

公开(公告)日：2021-06-03

申请号：US17173405

申请日：2021-02-11

Applicant: Micron Technology, Inc.

Inventor： Rohit Kothari ,  Jason C. McFarland ,  Jason Reece ,  David A. Kewley ,  Adam L. Olson

IPC: H01L27/11556 ,  H01L21/3213 ,  H01L21/311

Abstract: Methods of improving adhesion between a photoresist and conductive or insulating structures. The method comprises forming a slot through at least a portion of alternating conductive structures and insulating structures on a substrate. Portions of the conductive structures or of the insulating structures are removed to form recesses in the conductive structures or in the insulating structures. A photoresist is formed over the alternating conductive structures and insulating structures and within the slot. Methods of improving adhesion between a photoresist and a spin-on dielectric material are also disclosed, as well as methods of forming a staircase structure.