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1.发明申请Method of Forming Self-Aligned Air-Gaps Using Self-Aligned Capping Layer over Interconnect Lines 审中-公开在互连线上使用自对准覆盖层形成自对准空隙的方法公开(公告)号：US20070218677A1
公开(公告)日：2007-09-20
申请号：US11276801
申请日：2006-03-15
申请人： Manfred Engelhardt , Andreas Stich , Eugen Unger
发明人： Manfred Engelhardt , Andreas Stich , Eugen Unger
IPC分类号： H01L21/4763
CPC分类号： H01L21/76849 , H01L21/7682
摘要： A method for forming self-aligned air-gaps as IMD wherein the interconnect lines are covered with self-aligned capping layer and wherein the process of forming the capping layer is a maskless process is provided.
摘要翻译： 一种用于形成作为IMD的自对准气隙的方法，其中所述互连线被自对准覆盖层覆盖，并且其中形成所述覆盖层的工艺是无掩模工艺。
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公开(公告)号：US20070111431A1
公开(公告)日：2007-05-17
申请号：US11540502
申请日：2006-09-29
IPC分类号： H01L21/8242 , H01L29/94
摘要： An MIM capacitor includes a first capacitor electrode, which is formed in the surface of a first intermediate dielectric, a second intermediate dielectric, which is formed on the first intermediate dielectric and has an opening that exposes the first capacitor electrode, and a first electrically conducting diffusion barrier layer, which is formed on the surface of the exposed first capacitor electrode. On the diffusion barrier layer and on the side walls of the opening there is also formed a capacitor dielectric and a second capacitor electrode on top.
摘要翻译： MIM电容器包括形成在第一中间电介质的表面中的第一电容器电极，形成在第一中间电介质上并具有暴露第一电容器电极的开口的第二中间电介质，以及第一导电 扩散阻挡层，其形成在暴露的第一电容器电极的表面上。 在扩散阻挡层和开口的侧壁上，还在顶部形成电容电介质和第二电容器电极。
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公开(公告)号：US06946386B2
公开(公告)日：2005-09-20
申请号：US10854759
申请日：2004-05-25
IPC分类号： C23C18/31 , C23C28/02 , H01L21/4763
CPC分类号： C23C18/31 , C23C28/023
摘要： A method of forming an ultrathin homogenous metal layer that serves as base metallization for formation of contact locations and/or contact pads and/or wirings of an integrated electronic component. The method includes the steps of depositing a first metal layer on a substrate at least in regions, and producing a second metal layer on the first metal layer at least in regions, component(s) of the second metal layer have a more positive redox potential than component(s) of the first metal layer, wherein ultrathin homogenous deposition of the second metal layer is effected by wet-chemical, current-free, electrochemical redox processes by element exchange from one or more metal salts as oxidant with at least a top metal atomic layer of the first metal layer as reductant.
摘要翻译： 形成用于形成集成电子部件的接触位置和/或接触焊盘和/或布线的基底金属化的超薄均匀金属层的方法。 该方法包括以下步骤：至少在区域中在衬底上沉积第一金属层，并且至少在区域中在第一金属层上产生第二金属层，第二金属层的组分具有更正的氧化还原电位 其中第二金属层的超薄均匀沉积通过湿化学，无电流的电化学氧化还原过程通过元素交换从一种或多种金属盐作为氧化剂与至少一个顶部进行 第一金属层的金属原子层作为还原剂。
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公开(公告)号：US20050118342A1
公开(公告)日：2005-06-02
申请号：US10980011
申请日：2004-11-03
IPC分类号： B01J23/745 , B01J23/755 , B01J37/03 , C01B31/02 , C23C18/16 , C23C18/31 , B05D3/02
CPC分类号： B82Y30/00 , B01J23/745 , B01J23/755 , B01J37/03 , B82Y40/00 , C01B32/162 , C23C18/161 , C23C18/54
摘要： A process for the selective and areal deposition of a catalyst is disclosed, which is intended for the growth of nanotubes, on an interconnect line in an integrated circuit or chip. The process includes providing an acidic or alkaline aqueous solution of the catalyst; applying the solution to the interconnect line; and removing the excess solution.
摘要翻译： 公开了用于在集成电路或芯片的互连线上用于纳米管生长的选择性和面积沉积催化剂的方法。 该方法包括提供催化剂的酸性或碱性水溶液; 将解决方案应用于互连线; 并除去多余的溶液。
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公开(公告)号：US08709906B2
公开(公告)日：2014-04-29
申请号：US13342120
申请日：2012-01-02
IPC分类号： H01L21/20
摘要： An MIM capacitor includes a first capacitor electrode, which is formed in the surface of a first intermediate dielectric, a second intermediate dielectric, which is formed on the first intermediate dielectric and has an opening that exposes the first capacitor electrode, and a first electrically conducting diffusion barrier layer, which is formed on the surface of the exposed first capacitor electrode. On the diffusion barrier layer and on the side walls of the opening there is also formed a capacitor dielectric and a second capacitor electrode on top.
摘要翻译： MIM电容器包括形成在第一中间电介质的表面中的第一电容器电极，形成在第一中间电介质上并具有暴露第一电容器电极的开口的第二中间电介质，以及第一导电 扩散阻挡层，其形成在暴露的第一电容器电极的表面上。 在扩散阻挡层和开口的侧壁上，还在顶部形成电容器电介质和第二电容器电极。
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公开(公告)号：US20120100689A1
公开(公告)日：2012-04-26
申请号：US13342120
申请日：2012-01-02
IPC分类号： H01L21/02
摘要： An MIM capacitor includes a first capacitor electrode, which is formed in the surface of a first intermediate dielectric, a second intermediate dielectric, which is formed on the first intermediate dielectric and has an opening that exposes the first capacitor electrode, and a first electrically conducting diffusion barrier layer, which is formed on the surface of the exposed first capacitor electrode. On the diffusion barrier layer and on the side walls of the opening there is also formed a capacitor dielectric and a second capacitor electrode on top.
摘要翻译： MIM电容器包括形成在第一中间电介质的表面中的第一电容器电极，形成在第一中间电介质上并具有暴露第一电容器电极的开口的第二中间电介质，以及第一导电 扩散阻挡层，其形成在暴露的第一电容器电极的表面上。 在扩散阻挡层和开口的侧壁上，还在顶部形成电容器电介质和第二电容器电极。
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公开(公告)号：US08093637B2
公开(公告)日：2012-01-10
申请号：US11540502
申请日：2006-09-29
IPC分类号： H01L29/94
摘要： An MIM capacitor includes a first capacitor electrode, which is formed in the surface of a first intermediate dielectric, a second intermediate dielectric, which is formed on the first intermediate dielectric and has an opening that exposes the first capacitor electrode, and a first electrically conducting diffusion barrier layer, which is formed on the surface of the exposed first capacitor electrode. On the diffusion barrier layer and on the side walls of the opening there is also formed a capacitor dielectric and a second capacitor electrode on top.
摘要翻译： MIM电容器包括形成在第一中间电介质的表面中的第一电容器电极，形成在第一中间电介质上并具有暴露第一电容器电极的开口的第二中间电介质，以及第一导电 扩散阻挡层，其形成在暴露的第一电容器电极的表面上。 在扩散阻挡层和开口的侧壁上，还在顶部形成电容器电介质和第二电容器电极。
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公开(公告)号：US08877631B2
公开(公告)日：2014-11-04
申请号：US13110022
申请日：2011-05-18
IPC分类号： H01L21/4763 , H01L23/522 , H01L23/532 , H01L21/768 , H01L27/108
CPC分类号： H01L21/7681 , H01L21/7682 , H01L23/5222 , H01L23/53295 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： An interconnect arrangement and fabrication method are described. The interconnect arrangement includes an electrically conductive mount substrate, a dielectric layer formed on the mount substrate, and an electrically conductive interconnect formed on the dielectric layer. At least a portion of the dielectric layer under the interconnect contains a cavity. To fabricate the interconnect arrangement, a sacrificial layer is formed on the mount substrate and the interconnect layer is formed on the sacrificial layer. The interconnect layer and the sacrificial layer are structured to produce a structured interconnect on the structured sacrificial layer. A porous dielectric layer is formed on a surface of the mount substrate and of the structured interconnect as well as the sacrificial layer. The sacrificial layer is then removed to form the cavity under the interconnect.
摘要翻译： 描述了互连装置和制造方法。 互连装置包括导电安装基板，形成在安装基板上的电介质层和形成在电介质层上的导电布线。 互连下方的电介质层的至少一部分包含空腔。 为了制造互连布置，在安装基板上形成牺牲层，并且在牺牲层上形成互连层。 互连层和牺牲层被构造成在结构化牺牲层上产生结构化互连。 在安装基板和结构化互连的表面以及牺牲层上形成多孔电介质层。 然后去除牺牲层以在互连下形成空腔。
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9.发明授权Semiconductor devices having insulating substrates and methods of formation thereof 有权具有绝缘基板的半导体器件及其形成方法公开(公告)号：US08722514B2
公开(公告)日：2014-05-13
申请号：US13007892
申请日：2011-01-17
CPC分类号： H01L43/14 , H01L21/78 , H01L21/84 , H01L23/3121 , H01L23/3171 , H01L23/3178 , H01L23/3185 , H01L24/06 , H01L27/12 , H01L27/22 , H01L43/04 , H01L43/065 , H01L43/12 , H01L2224/04042 , H01L2224/05553 , H01L2224/48091 , H01L2224/48463 , H01L2224/73265 , H01L2924/01322 , H01L2924/10253 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/15788 , H01L2924/181 , H01L2924/3011 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： In one embodiment, a semiconductor device includes a glass substrate, a semiconductor substrate disposed on the glass substrate, and a magnetic sensor disposed within and/or over the semiconductor substrate.
摘要翻译： 在一个实施例中，半导体器件包括玻璃衬底，设置在玻璃衬底上的半导体衬底和设置在半导体衬底内和/或之上的磁传感器。
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公开(公告)号：US20130189830A1
公开(公告)日：2013-07-25
申请号：US13355003
申请日：2012-01-20
IPC分类号： H01L21/78
CPC分类号： H01L21/568 , H01L21/31138 , H01L21/561 , H01L21/563 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L23/3114 , H01L2221/68327 , H01L2221/6834 , H01L2924/0002 , H01L2924/00
摘要： In accordance with an embodiment of the present invention, a method of fabricating a semiconductor device includes forming a trench from a top surface of a substrate having a device region. The device region is adjacent to the top surface than an opposite bottom surface. The trench surrounds the sidewalls of the device region. The trench is filled with an adhesive. An adhesive layer is formed over the top surface of the substrate. A carrier is attached with the adhesive layer. The substrate is thinned from the bottom surface to expose at least a portion of the adhesive and a back surface of the device region. The adhesive layer is removed and adhesive is etched to expose a sidewall of the device region.
摘要翻译： 根据本发明的实施例，制造半导体器件的方法包括从具有器件区域的衬底的顶表面形成沟槽。 器件区域与顶表面相邻，而不是相对的底表面。 沟槽围绕设备区域的侧壁。 沟槽填充有粘合剂。 在衬底的顶表面上形成粘合剂层。 载体附着有粘合剂层。 衬底从底表面变薄以暴露粘合剂的至少一部分和器件区域的后表面。 去除粘合剂层并蚀刻粘合剂以露出装置区域的侧壁。
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