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9 条记录 (耗时 0.019 秒)

    Bus system
    1.
    发明申请
    Bus system 审中-公开
    总线系统

    公开(公告)号：US20060181437A1

    公开(公告)日：2006-08-17

    申请号：US11262960

    申请日：2005-11-01

    申请人： Martin Brox ,  Michael Markert ,  Manfred Plan ,  Peter Schrogmeier

    发明人： Martin Brox ,  Michael Markert ,  Manfred Plan ,  Peter Schrogmeier

    IPC分类号： H03M7/00

    CPC分类号： G06F13/4045 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The invention relates to a procedure for operating a bus system, as well as a bus system with a line, and two adjoining lines, whereby the lines each comprise two line sections, which are connected with one another by means of a line amplifier and/or buffer device, and whereby the line amplifier and/or buffer device connected with the line sections of the line is constructed as an inverting line amplifier and/or buffer device, and the line amplifier and/or buffer devices connected with the line sections of the adjoining lines are constructed as non-inverting line amplifier and/or buffer devices, or vice versa.

    摘要翻译： 本发明涉及一种用于操作总线系统的程序，以及具有线路的总线系统和两条相邻的线路，其中线路各自包括两个线路段，它们通过线路放大器和/ 或缓冲器件，并且由此将与线路的线路部分连接的线路放大器和/或缓冲器构造为反相线路放大器和/或缓冲器件，并且线路放大器和/或缓冲器件与线路部分 邻接的线路被构造为非反相线路放大器和/或缓冲器件，反之亦然。

    Method and apparatus for generating a second signal having a clock based on a second clock from a first signal having a first clock
    3.
    发明申请
    Method and apparatus for generating a second signal having a clock based on a second clock from a first signal having a first clock 审中-公开

    公开(公告)号：US20060149989A1

    公开(公告)日：2006-07-06

    申请号：US11367218

    申请日：2006-03-03

    申请人： Thilo Marx ,  Peter Schrogmeier

    发明人： Thilo Marx ,  Peter Schrogmeier

    IPC分类号： G06F1/06

    CPC分类号： G06F5/06 ,  H03K5/135 ,  H04L7/0008

    摘要： An apparatus for generating a second signal having a clock based on a second clock from a first signal with a first clock comprises first and second means for sampling the first signal to determine whether the first signal has a predetermined logic state, wherein first means samples the first signal with the second clock, and second means samples the first signal with a clock phase shifted to the second clock. Means for generating the second signal generates the second signal based on the second clock if it has been determined by at least one means for sampling that the first signal has the predetermined state. Especially for time critical applications, such as a DDR-RAM, a valuable latency saving is provided by the present invention.

    Method and integrated circuit for determining the state of a resistivity changing memory cell
    4.
    发明授权
    Method and integrated circuit for determining the state of a resistivity changing memory cell 失效
    用于确定电阻率变化的存储单元的状态的方法和集成电路

    公开(公告)号：US07751231B2

    公开(公告)日：2010-07-06

    申请号：US12115433

    申请日：2008-05-05

    申请人： Peter Schrogmeier ,  Ulrich Klostermann

    发明人： Peter Schrogmeier ,  Ulrich Klostermann

    IPC分类号： G11C11/00

    CPC分类号： G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607

    摘要： A method and an integrated circuit for determining the state of a resistivity changing memory cell. In one embodiment the method includes detecting a first resistance of the resistivity changing memory cell, determining whether the first resistance value is smaller than a predetermined threshold value thereby determining a first result value, initializing the resistivity changing memory cell into one of at least four resistivity changing memory states, detecting a second resistance value of the resistivity changing memory cell, determining whether the second resistance value is smaller than the predetermined threshold value determining a second result value, and determining the state of the resistivity changing memory cell state using the first and the second result values.

    摘要翻译： 一种用于确定电阻率变化存储单元的状态的方法和集成电路。 在一个实施例中，该方法包括检测电阻率变化存储单元的第一电阻，确定第一电阻值是否小于预定阈值，由此确定第一结果值，将电阻率变化存储单元初始化为至少四个电阻率 改变存储器状态，检测电阻率变化存储单元的第二电阻值，确定第二电阻值是否小于确定第二结果值的预定阈值，以及使用第一和第二电阻值确定电阻率变化存储单元状态的状态， 第二个结果值。

    Integrated memory
    5.
    发明授权
    Integrated memory 有权
    集成内存

    公开(公告)号：US06101141A

    公开(公告)日：2000-08-08

    申请号：US344922

    申请日：1999-06-28

    申请人： Sabine Schoniger ,  Peter Schrogmeier ,  Thomas Hein ,  Stefan Dietrich ,  Thilo Marx

    发明人： Sabine Schoniger ,  Peter Schrogmeier ,  Thomas Hein ,  Stefan Dietrich ,  Thilo Marx

    IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/02

    CPC分类号： G11C7/1048 ,  G11C11/4096 ,  G11C7/1006

    摘要： The integrated memory has a data line pair, which is connected to a bit line pair via at least one differential amplifier. In addition, it has a control unit for setting first potential states on the data line pair which correspond to the differential signals of data to be written to the memory cells, and for setting at least one second potential state on the data line pair which does not correspond to any datum to be written to the memory cells. Furthermore, it has a detector unit having two inputs connected to the data line pair. The detector unit initiates a specific control function when the second potential state of the data line pair occurs.

    摘要翻译： 集成存储器具有数据线对，其经由至少一个差分放大器连接到位线对。 此外，它具有控制单元，用于设置数据线对上对应于要写入存储单元的数据的差分信号的第一电位状态，并且在数据线对上设置至少一个第二电位状态 不对应于要写入存储单元的任何数据。 此外，它具有检测器单元，其具有连接到数据线对的两个输入。 当发生数据线对的第二电位状态时，检测器单元启动特定的控制功能。

    Method and circuit arrangement for resetting an integrated circuit
    8.
    发明申请
    Method and circuit arrangement for resetting an integrated circuit 有权
    用于复位集成电路的方法和电路装置

    公开(公告)号：US20050253638A1

    公开(公告)日：2005-11-17

    申请号：US11117736

    申请日：2005-04-29

    申请人： Stefan Dietrich ,  Thomas Hein ,  Patrick Heyne ,  Peter Schrogmeier

    发明人： Stefan Dietrich ,  Thomas Hein ,  Patrick Heyne ,  Peter Schrogmeier

    IPC分类号： G06F1/24 ,  G11C5/14 ,  G11C11/4072 ,  H01L21/82 ,  H03K5/1534 ,  H03L7/00

    CPC分类号： G06F1/24 ,  H03K5/1534

    摘要： The invention relates to a method for resetting at least one circuit part of an integrated circuit, in particular a synchronous semiconductor memory, in which a clock signal and a clock signal that is inverted with respect to the latter are provided in order to clock the integrated circuit, and in which, when a reset condition is present, an item of reset information is coded onto the clock signal or onto the inverted clock signal. The invention also relates to a circuit arrangement for carrying out the method according to the invention, having a clock suppression device and a decoder circuit, which is intended to extract the reset information from the clock signal or from the inverted clock signal.

    摘要翻译： 本发明涉及一种用于复位集成电路，特别是同步半导体存储器的至少一个电路部分的方法，其中提供时钟信号和相对于后者反相的时钟信号，以便对集成电路 电路，并且当存在复位条件时，将复位信息的项目编码到时钟信号或反相时钟信号上。 本发明还涉及用于执行根据本发明的方法的电路装置，其具有时钟抑制装置和解码器电路，其用于从时钟信号或反相时钟信号中提取复位信息。

    Integrated memory
    9.
    发明授权
    Integrated memory 有权
    集成内存

    公开(公告)号：US6028815A

    公开(公告)日：2000-02-22

    申请号：US258940

    申请日：1999-03-01

    申请人： Sabine Schoniger ,  Peter Schrogmeier ,  Thomas Hein ,  Stefan Dietrich

    发明人： Sabine Schoniger ,  Peter Schrogmeier ,  Thomas Hein ,  Stefan Dietrich

    IPC分类号： G11C7/10 ,  G11C8/00 ,  G11C8/14

    CPC分类号： G11C7/1006 ,  G11C8/00 ,  G11C8/14

    摘要： The integrated memory has byte selection lines for selecting all the bit lines of a respective byte, as well as masking signals that are allocated to the respective byte of at least one word. In addition, the memory has a column decoder with outputs which are connected to the word selection lines, each of which, when addressed, causes all the byte selection lines for one of the words to be simultaneously selected if none of the masking signals are active. The masking signals, when activated, prevent the addressed word selection line from selecting the byte selection lines, allocated to a corresponding byte, for a corresponding word.

    摘要翻译： 集成存储器具有用于选择相应字节的所有位线的字节选择线以及分配给至少一个字的相应字节的屏蔽信号。 此外，存储器具有列解码器，其具有连接到字选择线的输出，每个字选择线在寻址时都使得如果没有一个屏蔽信号有效则同时选择一个字的所有字节选择线 。 屏蔽信号被激活时，防止寻址字选择线选择分配给相应字节的字节选择线作为相应字。