公开(公告)号：US08835906B2

公开(公告)日：2014-09-16

申请号：US13310522

申请日：2011-12-02

申请人： Masahiko Hata ,  Tomoyuki Takada ,  Sadanori Yamanaka ,  Taro Itatani

发明人： Masahiko Hata ,  Tomoyuki Takada ,  Sadanori Yamanaka ,  Taro Itatani

IPC分类号： H01L31/0352 ,  H01L31/18 ,  H01L31/103 ,  H01L27/144 ,  H01L31/052 ,  H01L31/0392 ,  G01J5/02

CPC分类号： H01L27/1446 ,  G01J5/024 ,  H01L31/0392 ,  H01L31/0543 ,  H01L31/1035 ,  H01L31/1852 ,  Y02E10/52 ,  Y02E10/544 ,  Y02P70/521

摘要： A sensor includes: a base wafer containing silicon; a seed member provided directly or indirectly on the base wafer; and a photothermal absorber that is made of a Group 3-5 compound semiconductor lattice-matching or pseudo lattice-matching the seed member and being capable of generating a carrier upon absorbing light or heat, where the photothermal absorber outputs an electric signal in response to incident light to be introduced into the photothermal absorber or heat to be applied to the photothermal absorber. A semiconductor wafer includes: a base wafer containing silicon; a seed member provided directly or indirectly on the base wafer; and a photothermal absorber that is made of a Group 3-5 compound semiconductor lattice-matching or pseudo lattice-matching the seed member and being capable of generating a carrier upon absorbing light or heat.

摘要翻译： 传感器包括：含有硅的基底晶片; 种子构件直接或间接地设置在基底晶片上; 以及由第3-5族化合物半导体晶格匹配或伪晶格匹配种子构件并且能够在吸收光或热时产生载体的光热吸收体，其中光热吸收体输出响应于 入射到光热吸收器中的入射光或被加到光热吸收器上的热量。 半导体晶片包括：含有硅的基底晶片; 种子构件直接或间接地设置在基底晶片上; 以及由3-5族化合物半导体晶格匹配或伪晶格匹配种子构件制成并且能够在吸收光或热时产生载体的光热吸收剂。

公开(公告)号：US08823141B2

公开(公告)日：2014-09-02

申请号：US13255648

申请日：2010-03-08

申请人： Tomoyuki Takada ,  Masahiko Hata ,  Sadanori Yamanaka

发明人： Tomoyuki Takada ,  Masahiko Hata ,  Sadanori Yamanaka

IPC分类号： H01L29/20 ,  H01L21/02

CPC分类号： H01L21/0237 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02463 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02642 ,  H01L29/107 ,  H01L29/73 ,  H01L29/7371 ,  H01L29/772

摘要： The semiconductor wafer includes: a base wafer; and an inhibition layer that is disposed on the base wafer as one piece or to be separate portions from each other, and inhibits growth of a crystal of a compound semiconductor, where the inhibition layer has a plurality of first opening regions that have a plurality of openings penetrating the inhibition layer and leading to the base wafer, each of the plurality of first opening regions includes therein a plurality of first openings disposed in the same arrangement, some of the plurality of first openings are first element forming openings each provided with a first compound semiconductor on which an electronic element is to be formed, and the other of the plurality of first openings are first dummy openings in which no electronic element is to be formed.

摘要翻译： 半导体晶片包括：基底晶片; 以及抑制层，其一体地设置在所述基底晶片上或者彼此分离，并且抑制化合物半导体的晶体的生长，其中所述抑制层具有多个第一开口区域，所述第一开口区域具有多个 穿过所述抑制层并通向所述基底晶片的开口，所述多个第一开口区域中的每一个在其中包括设置在相同布置中的多个第一开口，所述多个第一开口中的一些是第一元件形成开口，每个元件形成开口设置有第一 其上形成有电子元件的复合半导体，并且多个第一开口中的另一个是其中不形成电子元件的第一虚拟开口。

公开(公告)号：US08716836B2

公开(公告)日：2014-05-06

申请号：US12811011

申请日：2008-12-26

申请人： Tomoyuki Takada ,  Sadanori Yamanaka ,  Masahiko Hata ,  Taketsugu Yamamoto ,  Kazumi Wada

发明人： Tomoyuki Takada ,  Sadanori Yamanaka ,  Masahiko Hata ,  Taketsugu Yamamoto ,  Kazumi Wada

IPC分类号： H01L21/331 ,  H01L29/737

CPC分类号： H01L21/8258 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02546 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/8252 ,  H01L29/66318

摘要： A high-quality GaAs-type crystal thin film using an inexpensive Si wafer with good thermal release characteristics is achieved. Provided is a semiconductor wafer comprising an Si wafer; an inhibiting layer that is formed on the wafer and that inhibits crystal growth, the inhibiting layer including a covering region that covers a portion of the wafer and an open region that does not cover a portion of the wafer within the covering region; a Ge layer that is crystal-grown in the open region; and a functional layer that is crystal-grown on the Ge layer. The Ge layer may be formed by annealing with a temperature and duration that enables movement of crystal defects, and the annealing is repeated a plurality of times.

摘要翻译： 实现了具有良好热释放特性的廉价Si晶片的高质量GaAs型晶体薄膜。 提供了包括Si晶片的半导体晶片; 所述抑制层形成在所述晶片上并且抑制晶体生长，所述抑制层包括覆盖所述晶片的一部分的覆盖区域和不覆盖所述覆盖区域内的所述晶片的一部分的开放区域; 在开放区域晶体生长的Ge层; 以及在Ge层上晶体生长的功能层。 Ge层可以通过使得能够移动晶体缺陷的温度和持续时间退火而形成，并且退火重复多次。

公开(公告)号：US08633496B2

公开(公告)日：2014-01-21

申请号：US13310451

申请日：2011-12-02

申请人： Masahiko Hata ,  Sadanori Yamanaka ,  Tomoyuki Takada

发明人： Masahiko Hata ,  Sadanori Yamanaka ,  Tomoyuki Takada

IPC分类号： H01L27/15

CPC分类号： H01L27/1446 ,  H01L21/02439 ,  H01L21/02441 ,  H01L21/02502 ,  H01L21/02521 ,  H01L21/02524 ,  H01L27/14601 ,  H01L27/15 ,  H01L27/156 ,  H01L29/161 ,  H01L29/267 ,  H01L29/7371 ,  H01S5/021

摘要： Provided is an optical device including a base wafer containing silicon, a plurality of seed crystals disposed on the base wafer, and a plurality of Group 3-5 compound semiconductors lattice-matching or pseudo lattice-matching the plurality of seed crystals. At least one of the Group 3-5 compound semiconductors has a photoelectric semiconductor formed therein, the photoelectric semiconductor including a light emitting semiconductor that emits light in response to a driving current supplied thereto or a light receiving semiconductor that generates a photocurrent in response to light applied thereto, and at least one of the plurality of Group 3-5 compound semiconductors other than the Group 3-5 compound semiconductor having the photoelectric semiconductor has a heterojunction transistor formed therein.

摘要翻译： 提供了一种光学器件，其包括含有硅的基底晶片，设置在基底晶片上的多个晶种，以及多个晶格匹配或伪晶格匹配多个晶种的3-5族化合物半导体。 第3-5组化合物半导体中的至少一个具有形成在其中的光电半导体，该光电半导体包括响应于提供的驱动电流而发光的发光半导体或响应于光产生光电流的光接收半导体 并且除了具有光电半导体的组3-5化合物半导体之外的多个3-5族化合物半导体中的至少一个具有形成在其中的异质结晶体管。

公开(公告)号：US08507952B2

公开(公告)日：2013-08-13

申请号：US13495746

申请日：2012-06-13

申请人： Sadanori Yamanaka ,  Tomoyuki Takada ,  Masahiko Hata

发明人： Sadanori Yamanaka ,  Tomoyuki Takada ,  Masahiko Hata

IPC分类号： H01L21/02

CPC分类号： H01L21/02639 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02546

摘要： To improve the flatness of the surface and improve the reliability of a semiconductor device when expitaxially growing semiconductor crystal layers of different types on a single silicon wafer, provided is a semiconductor wafer which includes: a base wafer having a silicon crystal in the surface thereof, the silicon crystal having a first dent and a second dent; a first Group IVB semiconductor crystal located in the first dent and exposed; a second Group IVB semiconductor crystal located in the second dent; and a Group III-V compound semiconductor crystal located above the second Group IVB semiconductor crystal in the second dent and exposed.

摘要翻译： 为了提高表面的平坦度，提高在单晶硅晶片上外延生长不同种类的半导体晶体层时的半导体器件的可靠性，提供了一种半导体晶片，其包括：在其表面具有硅晶体的基底晶片， 所述硅晶体具有第一凹陷和第二凹陷; 第一组IVB半导体晶体位于第一凹陷中并暴露; 位于第二凹陷中的第二组IVB半导体晶体; 以及位于第二凹陷中的第二IVB族半导体晶体上方并暴露的III-V族化合物半导体晶体。

公开(公告)号：US08809908B2

公开(公告)日：2014-08-19

申请号：US12811038

申请日：2008-12-26

申请人： Tomoyuki Takada ,  Sadanori Yamanaka ,  Masahiko Hata

发明人： Tomoyuki Takada ,  Sadanori Yamanaka ,  Masahiko Hata

IPC分类号： H01L21/20

CPC分类号： H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02516 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/8258 ,  H01L27/0605 ,  H01L29/22 ,  H01L29/66318 ,  H01L29/737 ,  H01L29/7786

摘要： A high-quality GaAs-type crystal thin film using an inexpensive Si wafer with good thermal release characteristics is achieved. Provided is a semiconductor wafer comprising an Si wafer; a Ge layer that is crystal-grown on the wafer and shaped as an isolated island; a buffer layer that is crystal-grown on the Ge layer and is a group 3-5 compound semiconductor layer containing P; and a functional layer that is crystal-grown on the buffer layer. The Ge layer may be shaped as an island having a size that does not exceed double a distance moved by crystal defects as a result of annealing the Ge layer at a certain temperature for a certain time. The Ge layer may be shaped as an island having a size for which stress due to a difference relative to a thermal expansion coefficient of Si, which is material of the wafer, does not cause crystal defects when the Ge layer is annealed at a certain temperature.

摘要翻译： 实现了具有良好热释放特性的廉价Si晶片的高质量GaAs型晶体薄膜。 提供了包括Si晶片的半导体晶片; 在晶片上晶体生长并形成孤岛的Ge层; 在Ge层上晶体生长并且是含有P的3-5族化合物半导体层的缓冲层; 以及在缓冲层上晶体生长的功能层。 Ge层可以成形为岛，其尺寸不超过由晶格缺陷移动的距离的两倍，这是由于Ge层在一定温度下退火一定时间的结果。 Ge层可以成形为具有如下尺寸的岛，即当Ge层在一定温度下退火时，具有相对于作为晶片材料的Si的热膨胀系数的差的应力不会引起晶体缺陷的尺寸 。

公开(公告)号：US08729677B2

公开(公告)日：2014-05-20

申请号：US13131498

申请日：2009-11-26

申请人： Sadanori Yamanaka ,  Masahiko Hata ,  Tomoyuki Takada

发明人： Sadanori Yamanaka ,  Masahiko Hata ,  Tomoyuki Takada

IPC分类号： H01L29/04

CPC分类号： H01L21/8258 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02636

摘要： A semiconductor wafer including: a base wafer; a seed crystal disposed on the base wafer; a compound semiconductor disposed above the seed crystal; and a high resistance layer disposed between the seed crystal and the compound semiconductor, the high resistance layer having a larger resistivity than the seed crystal, and the seed crystal lattice matching or pseudo lattice matching the compound semiconductor is provided.

摘要翻译： 一种半导体晶片，包括：基底晶片; 设置在基底晶片上的晶种; 设置在晶种上方的化合物半导体; 以及设置在晶种和化合物半导体之间的高电阻层，具有比晶种更大的电阻率的高电阻层，并且提供晶种匹配或伪晶格匹配化合物半导体。

公开(公告)号：US20110012175A1

公开(公告)日：2011-01-20

申请号：US12811073

申请日：2008-12-26

申请人： Tomoyuki Takada ,  Sadanori Yamanaka ,  Masahiko Hata ,  Taketsugu Yamamoto ,  Kazumi Wada

发明人： Tomoyuki Takada ,  Sadanori Yamanaka ,  Masahiko Hata ,  Taketsugu Yamamoto ,  Kazumi Wada

IPC分类号： H01L29/73 ,  H01L29/12 ,  H01L21/20

CPC分类号： H01L21/8258 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02516 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/66242 ,  H01L29/66318 ,  H01L29/737 ,  H01L29/7786

摘要： A high-quality GaAs-type crystal thin film using an inexpensive Si wafer with good thermal release characteristics is achieved. Provided is a semiconductor wafer comprising an Si wafer; a Ge layer that is crystal-grown on the wafer and shaped as an isolated island; and a functional layer that is crystal-grown on the Ge layer. The Ge layer may be shaped as an island having a size that docs not exceed double a distance moved by crystal defects as a result of annealing the Ge layer at a certain temperature for a certain time. The Ge layer may be shaped as an island having a size for which stress due to a difference relative to a thermal expansion coefficient of Si, which is material of the wafer, does not cause crystal dejects when the Ge layer is annealed at a certain temperature.

摘要翻译： 实现了具有良好热释放特性的廉价Si晶片的高质量GaAs型晶体薄膜。 提供了包括Si晶片的半导体晶片; 在晶片上晶体生长并形成隔离岛的Ge层; 以及在Ge层上晶体生长的功能层。 Ge层可以被成形为岛，其尺寸不超过由晶格缺陷移动的距离的两倍，这是由于Ge层在一定温度下退火一定时间的结果。 Ge层可以成形为岛，其具有如下尺寸：当Ge层在一定温度下退火时，由于与作为晶片的材料的Si的热膨胀系数的差异而产生的应力不会引起晶体磨损的尺寸 。

公开(公告)号：US20100308376A1

公开(公告)日：2010-12-09

申请号：US12811011

申请日：2008-12-26

申请人： Tomoyuki Takada ,  Sadanori Yamanaka ,  Masahiko Hata ,  Taketsugu Yamamoto ,  Kazumi Wada

发明人： Tomoyuki Takada ,  Sadanori Yamanaka ,  Masahiko Hata ,  Taketsugu Yamamoto ,  Kazumi Wada

IPC分类号： H01L29/12 ,  H01L21/20 ,  H01L21/322

CPC分类号： H01L21/8258 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02546 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/8252 ,  H01L29/66318

摘要： A high-quality GaAs-type crystal thin film using an inexpensive Si wafer with good thermal release characteristics is achieved. Provided is a semiconductor wafer comprising an Si wafer; an inhibiting layer that is formed on the wafer and that inhibits crystal growth, the inhibiting layer including a covering region that covers a portion of the wafer and an open region that does not cover a portion of the wafer within the covering region; a Ge layer that is crystal-grown in the open region; and a functional layer that is crystal-grown on the Ge layer. The Ge layer may be formed by annealing with a temperature and duration that enables movement of crystal defects, and the annealing is repeated a plurality of times.

摘要翻译： 实现了具有良好热释放特性的廉价Si晶片的高质量GaAs型晶体薄膜。 提供了包括Si晶片的半导体晶片; 所述抑制层形成在所述晶片上并且抑制晶体生长，所述抑制层包括覆盖所述晶片的一部分的覆盖区域和不覆盖所述覆盖区域内的所述晶片的一部分的开放区域; 在开放区域晶体生长的Ge层; 以及在Ge层上晶体生长的功能层。 Ge层可以通过使得能够移动晶体缺陷的温度和持续时间退火而形成，并且退火重复多次。

公开(公告)号：US20110316051A1

公开(公告)日：2011-12-29

申请号：US13255648

申请日：2010-03-08

申请人： Tomoyuki Takada ,  Masahiko Hata ,  Sadanori Yamanaka

发明人： Tomoyuki Takada ,  Masahiko Hata ,  Sadanori Yamanaka

IPC分类号： H01L29/165 ,  H01L21/20

CPC分类号： H01L21/0237 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02463 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02642 ,  H01L29/107 ,  H01L29/73 ,  H01L29/7371 ,  H01L29/772

摘要： The semiconductor wafer includes: a base wafer; and an inhibition layer that is disposed on the base wafer as one piece or to be separate portions from each other, and inhibits growth of a crystal of a compound semiconductor, where the inhibition layer has a plurality of first opening regions that have a plurality of openings penetrating the inhibition layer and leading to the base wafer, each of the plurality of first opening regions includes therein a plurality of first openings disposed in the same arrangement, some of the plurality of first openings are first element forming openings each provided with a first compound semiconductor on which an electronic element is to be formed, and the other of the plurality of first openings are first dummy openings in which no electronic element is to be formed.

摘要翻译： 半导体晶片包括：基底晶片; 以及抑制层，其一体地设置在所述基底晶片上或者彼此分离，并且抑制化合物半导体的晶体的生长，其中所述抑制层具有多个第一开口区域，所述第一开口区域具有多个 穿过所述抑制层并通向所述基底晶片的开口，所述多个第一开口区域中的每一个在其中包括设置在相同布置中的多个第一开口，所述多个第一开口中的一些是第一元件形成开口，每个元件形成开口设置有第一 其上形成有电子元件的复合半导体，并且多个第一开口中的另一个是其中不形成电子元件的第一虚拟开口。