公开(公告)号：US20080223607A1

公开(公告)日：2008-09-18

申请号：US12026838

申请日：2008-02-06

申请人： Masaki MURAMATSU ,  Shinji Yuri ,  Kazuhiro Urashima ,  Hiroshi Yamamoto ,  Toshitake Seki ,  Motohiko Sato

发明人： Masaki MURAMATSU ,  Shinji Yuri ,  Kazuhiro Urashima ,  Hiroshi Yamamoto ,  Toshitake Seki ,  Motohiko Sato

IPC分类号： H05K1/16

CPC分类号： H01G2/06 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/10 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： An intermediate board has a board core formed by a main core body and a sub-core portion. The main core body has a plate-like shape and includes an open sub-core housing portion in which the sub-core portion is housed. A first terminal array of the board core has an area that overlaps an orthogonal projection of the sub-core portion. The latter incorporates a laminated ceramic capacitor formed by first and second conductor layers with a ceramic (dielectric) layer therebetween. The first layer is connected to first and second side terminals of a first type while the second layer is connected to first and second side terminals of a second type. The housing portion has an inner edge which, in cross section, is of a quadrate shape, and a radius portion is formed at each corner having a dimension of between 0.1 and 2 mm.

摘要翻译： 中间板具有由主芯体和副芯部形成的板芯。 主芯体具有板状形状，并且包括其中容纳有副芯部的开放子芯容纳部。 板芯的第一端子阵列具有与子芯部的正交突起重叠的区域。 后者包括由其间具有陶瓷（电介质）层的第一和第二导体层形成的层叠陶瓷电容器。 第一层连接到第一类型的第一和第二侧端子，而第二层连接到第二类型的第一和第二侧端子。 壳体部分具有横截面为正方形的内边缘，并且在每个角部处形成具有0.1至2mm的尺寸的半径部分。

公开(公告)号：US20100139090A1

公开(公告)日：2010-06-10

申请号：US12706695

申请日：2010-02-16

申请人： Masaki MURAMATSU ,  Shinji YURI ,  Makoto ORIGUCHI ,  Kazuhiro URASHIMA

发明人： Masaki MURAMATSU ,  Shinji YURI ,  Makoto ORIGUCHI ,  Kazuhiro URASHIMA

IPC分类号： H05K3/10

CPC分类号： H01L21/6835 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01055 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/351 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/142 ,  H05K1/162 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/096 ,  H05K2201/10674 ,  H05K2201/10712 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401

摘要： A wiring board comprising: a core board including a core body and a ceramic sub-core which is accommodated in a sub-core accommodation space that is a through-hole that communicates with major surfaces of the core body or a recess having an opening in a first major surface of the core body; and wiring laminates each formed by resin insulating layers and conductor layers laminated on each of major surfaces of the core board, wherein: a groove-filling portion which fills a gap between the core body and the ceramic sub-core is integral with a lowest resin insulating layer of the first-major-surface-side wiring laminate; and via conductors that are connected to respective conductor patterns formed on a first major surface of the ceramic sub-core penetrate through the lowest resin insulating layer.

摘要翻译： 一种布线板，包括：芯板，其包括芯体和陶瓷子芯，所述芯体容纳在与所述芯体的主表面连通的通孔的子芯容纳空间中，或者具有开口的凹部 核心体的第一个主要表面; 以及由层叠在芯板的各主表面上的树脂绝缘层和导体层形成的布线层叠体，其中，填充芯体与陶瓷副芯之间的间隙的沟槽填充部与最低树脂 第一主表面侧布线层叠体的绝缘层; 并且连接到形成在陶瓷子芯的第一主表面上的相应导体图案的通孔导体穿透最低树脂绝缘层。

公开(公告)号：US20120110839A1

公开(公告)日：2012-05-10

申请号：US13283269

申请日：2011-10-27

申请人： Kenji NISHIO ,  Masaki MURAMATSU ,  Masao IZUMI ,  Erina YAMADA ,  Hironori SATO

发明人： Kenji NISHIO ,  Masaki MURAMATSU ,  Masao IZUMI ,  Erina YAMADA ,  Hironori SATO

IPC分类号： H05K3/36

CPC分类号： H05K3/465 ,  H05K3/125 ,  H05K3/4664 ,  H05K2203/0139 ,  H05K2203/1476 ,  Y10T29/49126

摘要： Disclosed is a manufacturing method of a wiring board with at least one conduction layer and at least one resin insulation layer. The manufacturing method includes an opening forming step of forming openings in the resin insulation layer and a paste filling step of filling a copper paste into the openings to form the conduction layer from the copper paste.

摘要翻译： 公开了具有至少一个导电层和至少一个树脂绝缘层的布线板的制造方法。 该制造方法包括在树脂绝缘层中形成开口的开口形成步骤和将铜膏填充到开口中以从铜浆形成导电层的糊料填充步骤。

公开(公告)号：US20110232085A1

公开(公告)日：2011-09-29

申请号：US13025557

申请日：2011-02-11

申请人： Masaki MURAMATSU ,  Kenji NISHIO ,  Kazunaga HIGO ,  Hironori SATO ,  Takuya TORII ,  Masao IZUMI

发明人： Masaki MURAMATSU ,  Kenji NISHIO ,  Kazunaga HIGO ,  Hironori SATO ,  Takuya TORII ,  Masao IZUMI

IPC分类号： H05K3/40 ,  H05K3/10

CPC分类号： H05K3/465 ,  H05K3/0032 ,  H05K2203/0557 ,  H05K2203/108 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A method of fabricating a wiring board including at least one conductor layer and at least one resin insulating layer, the method including a wiring groove forming step of forming a wiring groove in the resin insulating layer by irradiating a surface of the resin insulating layer with a laser, and a wiring layer forming step of forming the conductor layer such that at least a portion of the conductor layer is embedded in the wiring groove to form a wiring layer in the wiring groove.

摘要翻译： 一种制造包括至少一个导体层和至少一个树脂绝缘层的布线板的方法，所述方法包括：布线槽形成步骤，通过用树脂绝缘层的表面照射树脂绝缘层的表面，在所述树脂绝缘层中形成布线槽 以及形成导体层的布线层形成步骤，使得导体层的至少一部分嵌入布线槽中，以在布线槽中形成布线层。

公开(公告)号：US20130032485A1

公开(公告)日：2013-02-07

申请号：US13564420

申请日：2012-08-01

申请人： Masaki MURAMATSU ,  Masao IZUMI ,  Kenji NISHIO ,  Hironori SATO

发明人： Masaki MURAMATSU ,  Masao IZUMI ,  Kenji NISHIO ,  Hironori SATO

IPC分类号： C23C28/00

CPC分类号： H05K3/465 ,  C25D3/38 ,  C25D5/48 ,  H05K3/045 ,  H05K2203/025

摘要： A method of fabricating a circuit board including at least one insulation layer and at least one wiring layer, the method including a first step of forming a wiring trench in a surface of the insulation layer, a second step of forming a conductor layer serving as the wiring layer in the wiring trench such that at least a portion of the conductor layer is embedded in the wiring trench, and a third step of cutting a surface of the conductor layer with a cutting tool to form the wiring layer.

摘要翻译： 一种制造包括至少一个绝缘层和至少一个布线层的电路板的方法，所述方法包括在所述绝缘层的表面中形成布线沟槽的第一步骤，形成用作所述绝缘层的导体层的第二步骤 布线沟槽中的布线层，使得导体层的至少一部分嵌入布线沟槽中;以及第三步骤，用切割工具切割导体层的表面以形成布线层。