公开(公告)号：US06239464B1

公开(公告)日：2001-05-29

申请号：US09226720

申请日：1999-01-07

申请人： Masanobu Tsuchitani ,  Keita Suzuki ,  Akihiko Osawa ,  Yoshiro Baba

发明人： Masanobu Tsuchitani ,  Keita Suzuki ,  Akihiko Osawa ,  Yoshiro Baba

IPC分类号： H01L29792

CPC分类号： H01L29/66666 ,  H01L29/42368 ,  H01L29/4238

摘要： A semiconductor device, which can have a uniform film on open ends of trenches by using materials having a different oxidation rate, and a fabrication method thereof are provided. The semiconductor device having trenches configured to have open ends covered with an oxidation film made of a material having an oxidation rate faster than that of a semiconductor substrate and a fabrication method thereof are provided.

摘要翻译： 提供一种半导体器件及其制造方法，该半导体器件可以通过使用具有不同氧化速率的材料在沟槽的开口端上具有均匀的膜。 具有沟槽的半导体器件被配置为具有用氧化速率快于半导体衬底的材料制成的氧化膜覆盖的开口端及其制造方法。

公开(公告)号：US6060747A

公开(公告)日：2000-05-09

申请号：US159122

申请日：1998-09-23

申请人： Hideki Okumura ,  Akihiko Osawa ,  Yoshiro Baba ,  Noboru Matsuda ,  Masanobu Tsuchitani

发明人： Hideki Okumura ,  Akihiko Osawa ,  Yoshiro Baba ,  Noboru Matsuda ,  Masanobu Tsuchitani

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/739

CPC分类号： H01L29/0696

摘要： A semiconductor device is characterized in that source electrode contact regions, each of which is formed of a first conductivity type source layer and a second conductivity type base layer in a surface of a semiconductor surface, are formed at respective intersectional points of a diagonally-arranged lattice, and in that a trench having a gate electrode buried therein is formed so as to snake through the contact regions alternately. By virtue of the structure, the trench arrangement and source/base simultaneous contact quality are improved, to thereby increase a trench density (channel density) per unit area.

摘要翻译： 半导体器件的特征在于，在对角线布置的各个交点处形成源极电极接触区域，每个源极电极接触区域由半导体表面的第一导电型源极层和第二导电型基极层形成， 并且具有埋入其中的具有栅电极的沟槽形成为交替地穿过接触区域。 通过该结构，提高了沟槽布置和源极/基极同时接触质量，从而增加了每单位面积的沟槽密度（沟道密度）。

公开(公告)号：US5578508A

公开(公告)日：1996-11-26

申请号：US426233

申请日：1995-04-21

申请人： Yoshiro Baba ,  Satoshi Yanagiya ,  Noboru Matsuda ,  Akihiko Osawa ,  Masanobu Tsuchitani

发明人： Yoshiro Baba ,  Satoshi Yanagiya ,  Noboru Matsuda ,  Akihiko Osawa ,  Masanobu Tsuchitani

IPC分类号： H01L21/302 ,  H01L21/265 ,  H01L21/266 ,  H01L21/306 ,  H01L21/336 ,  H01L29/78 ,  H01L21/304 ,  H01L21/76

CPC分类号： H01L29/7813 ,  H01L29/66734 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/7838

摘要： A channel region and a source region are formed on a surface of a substrate by double diffusion. A trench is formed so as to penetrate a part of the channel region and a part of the source region and reach the substrate. After an insulating film is formed on an inner wall of the trench, a polysilicon layer is buried up to an intermediate portion of the trench. In this state, channel ions are implanted in a side surface region of the trench, thereby depleting a channel region. Thereafter, a polysilicon layer for leading out a gate is buried in the trench.

摘要翻译： 通过双扩散在衬底的表面上形成沟道区域和源极区域。 形成沟槽，以便穿透沟道区域的一部分和源区域的一部分并到达衬底。 在沟槽的内壁上形成绝缘膜之后，将多晶硅层埋入沟槽的中间部分。 在这种状态下，沟道离子注入沟槽的侧表面区域，从而耗尽沟道区域。 此后，用于引出栅极的多晶硅层被埋在沟槽中。

公开(公告)号：US6031276A

公开(公告)日：2000-02-29

申请号：US950841

申请日：1997-10-15

申请人： Akihiko Osawa ,  Yoshiro Baba ,  Masanobu Tsuchitani ,  Shizue Hori

发明人： Akihiko Osawa ,  Yoshiro Baba ,  Masanobu Tsuchitani ,  Shizue Hori

IPC分类号： H01L29/74 ,  H01L21/265 ,  H01L21/266 ,  H01L21/322 ,  H01L21/329 ,  H01L29/32 ,  H01L29/861 ,  H01L26/30

CPC分类号： H01L29/66136 ,  H01L21/26506 ,  H01L21/266 ,  H01L29/32

摘要： A semiconductor device includes a plurality of defect layers separated from one another in the semiconductor layer. A distance separating any adjacent ones of the defect layers is kept such that they are prevented from contacting each other and those regions having effect of shortening a carrier lifetime overlap each other.

摘要翻译： 半导体器件包括在半导体层中彼此分离的多个缺陷层。 保持分离任何相邻的缺陷层的距离使得它们被防止彼此接触，并且那些具有缩短载流子寿命的作用的那些区域彼此重叠。

公开(公告)号：US06337498B1

公开(公告)日：2002-01-08

申请号：US09249296

申请日：1999-02-12

申请人： Shigeru Hasegawa ,  Hideo Matsuda ,  Yoshiro Baba ,  Masanobu Tsuchitani

发明人： Shigeru Hasegawa ,  Hideo Matsuda ,  Yoshiro Baba ,  Masanobu Tsuchitani

IPC分类号： H01L2994

CPC分类号： H01L29/7397 ,  H01L29/0696 ,  H01L29/4238

摘要： A semiconductor device such as an IGBT having trench gates in a form of stripes, and manufacturing method, wherein concentration of stresses in only a single direction is relieved and the generation of a leakage current and crystal defects in the IGBT is prevented. In one embodiment, the inside of a terminal area of an IGBT is divided into a single gate pad area and plural element areas by a wiring area. The respective element areas are arranged in such a manner that the directions of trench gates formed in the respective element areas cross at right angles with respect to the directions of trench gates of respective adjacent element areas.

摘要翻译： 诸如具有条形沟槽栅极的IGBT的半导体器件以及其中单个方向上的应力集中被释放并且防止了IGBT中产生漏电流和晶体缺陷的制造方法。 在一个实施例中，IGBT的端子区域的内部通过布线区域分成单个栅极焊盘区域和多个元件区域。 相应的元件区域被布置成使得形成在各个元件区域中的沟槽栅极的方向相对于各个相邻元件区域的沟槽栅极的方向成直角交叉。

公开(公告)号：US5770514A

公开(公告)日：1998-06-23

申请号：US787573

申请日：1997-01-22

申请人： Noboru Matsuda ,  Yoshiro Baba ,  Satoshi Yanagiya ,  Masanobu Tsuchitani

发明人： Noboru Matsuda ,  Yoshiro Baba ,  Satoshi Yanagiya ,  Masanobu Tsuchitani

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/423 ,  H01L29/739 ,  H01L29/772 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/7397 ,  H01L29/7813 ,  H01L29/4232 ,  H01L29/4238

摘要： In a vertical field effect transistor having a trench gate and a method of manufacturing the same according to the present invention, p-type base and n.sup.+ -type source diffusion layers are formed in this order in a surface region of an n.sup.31 -type epitaxial layer on an n.sup.+ -type semiconductor substrate. A trench is then provided to such a depth as to penetrate the diffusion layers. A dope polysilicon layer is deposited and buried into the trench with a gate insulation film interposed between them. The polysilicon layer is etched to have the same level as that of the entrance of the trench, and a dope polysilicon layer 18 is selectively grown thereon, thereby forming a trench gate in which an upper corner portion of the trench is not covered with a gate electrode. Consequently, the concentration of electric fields at the corner portion can be mitigated thereby to increase an absolute withstand voltage of the gate and the variations in threshold voltage can be suppressed in a BT test.

摘要翻译： 在根据本发明的具有沟槽栅的垂直场效应晶体管及其制造方法中，在n31型外延层的表面区域中依次形成p型基极和n +型源极扩散层 在n +型半导体衬底上。 然后将沟槽提供到穿透扩散层的深度。 将掺杂多晶硅层沉积并埋入沟槽中，并在其间插入栅极绝缘膜。 蚀刻多晶硅层以与沟槽的入口具有相同的电平，并且在其上选择性地生长掺杂多晶硅层18，从而形成沟槽栅极，其中沟槽的上角部分未被栅极覆盖 电极。 因此，可以减轻角部处的电场的集中，从而提高栅极的绝对耐受电压，并且可以在BT测试中抑制阈值电压的变化。

公开(公告)号：US6084263A

公开(公告)日：2000-07-04

申请号：US27727

申请日：1998-02-23

申请人： Masanobu Tsuchitani ,  Shizue Hori ,  Akihiko Osawa

发明人： Masanobu Tsuchitani ,  Shizue Hori ,  Akihiko Osawa

IPC分类号： H01L29/861 ,  H01L29/06 ,  H01L29/739 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7395 ,  H01L29/0611

摘要： The main characteristic feature of the invention is to prevent a leakage current from flowing when a planar type semiconductor device having a high breakdown voltage is reverse-biased. For example, a semiconductive film is formed on the surface of an n-type Si substrate between a second p-type base layer selectively formed on the surface of the Si substrate and a channel stop layer formed to surround the second p-type base layer at a predetermined interval. The dangling bond density of the semiconductive film is set at 1.25.times.1018 cm.sup.-3. With this structure, the discrete level in the band gap approach a continuum, and the time required to populate the trapping level in the semiconductive film with carriers is shortened.

摘要翻译： 本发明的主要特征是当具有高击穿电压的平面型半导体器件被反向偏置时，防止漏电流流动。 例如，在n型Si衬底的表面上形成半导体膜，该第二p型基极层选择性地形成在Si衬底表面上的第二p型基极层和形成为围绕第二p型基极层的沟道阻挡层 以预定间隔。 半导体膜的悬挂键密度设定为1.25×10 18 cm -3。 利用这种结构，带隙中的离散水平接近连续体，缩短了用载体填充半导体薄膜中的捕获水平所需的时间。

公开(公告)号：US20060145290A1

公开(公告)日：2006-07-06

申请号：US11294411

申请日：2005-12-06

申请人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Akihiko Osawa ,  Wataru Saito ,  Masakazu Yamaguchi ,  Ichiro Omura

发明人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Akihiko Osawa ,  Wataru Saito ,  Masakazu Yamaguchi ,  Ichiro Omura

IPC分类号： H01L29/00 ,  H01L21/425 ,  H01L21/336

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/7802

摘要： A semiconductor device includes a diffusion area formed in a semiconductor layer of a first conductive type. The diffusion area comprises first and second impurity diffusion areas of the first and second conductive types, respectively. The diffusion area has a first and second areas which are defined by an impurity concentration of the first and second impurity diffusion areas. A junction between the first and second area is formed in a portion in which the first and second impurity diffusion areas overlap each other. A period of the impurity concentration, in a planar direction of the semiconductor layer, of the first or second area is smaller than the maximum width, in the planar direction of the semiconductor layer, of the first and second impurity diffusion areas constituting the first or second area.

公开(公告)号：US06995426B2

公开(公告)日：2006-02-07

申请号：US10327937

申请日：2002-12-26

申请人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Akihiko Osawa ,  Wataru Saito ,  Masakazu Yamaguchi ,  Ichiro Omura

发明人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Akihiko Osawa ,  Wataru Saito ,  Masakazu Yamaguchi ,  Ichiro Omura

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/7802

摘要： A semiconductor device includes a diffusion area formed in a semiconductor layer of a first conductive type. The diffusion area comprises first and second impurity diffusion areas of the first and second conductive types, respectively. The diffusion area has a first and second areas which are defined by an impurity concentration of the first and second impurity diffusion areas. A junction between the first and second area is formed in a portion in which the first and second impurity diffusion areas overlap each other. A period of the impurity concentration, in a planar direction of the semiconductor layer, of the first or second area is smaller than the maximum width, in the planar direction of the semiconductor layer, of the first and second impurity diffusion areas constituting the first or second area.

摘要翻译： 半导体器件包括形成在第一导电类型的半导体层中的扩散区域。 扩散区域分别包括第一和第二导电类型的第一和第二杂质扩散区域。 扩散区域具有由第一和第二杂质扩散区域的杂质浓度限定的第一和第二区域。 第一和第二区域之间的结点形成在第一和第二杂质扩散区域彼此重叠的部分中。 在第一或第二区域的半导体层的平面方向上的杂质浓度的周期小于半导体层的平面方向上的构成第一或第二区域的第一和第二杂质扩散区域的最大宽度 第二区。

公开(公告)号：US20080299686A1

公开(公告)日：2008-12-04

申请号：US11871497

申请日：2007-10-12

申请人： Motoshige KOBAYASHI ,  Masanobu Echizenya ,  Shinya Takyu ,  Noriko Shimizu ,  Hideki Nozaki ,  Masanobu Tsuchitani

发明人： Motoshige KOBAYASHI ,  Masanobu Echizenya ,  Shinya Takyu ,  Noriko Shimizu ,  Hideki Nozaki ,  Masanobu Tsuchitani

IPC分类号： H01L21/66

CPC分类号： H01L22/12 ,  H01L21/30604 ,  H01L21/3065 ,  H01L22/20 ,  H01L29/66348

摘要： A method for manufacturing a semiconductor device, includes; measuring a within-wafer distribution of a physical quantity; and etching the wafer so that the physical quantity get close to constant within the wafer. Alternatively, a method for manufacturing a semiconductor device, includes, measuring a within-wafer distribution of a physical quantity of at least one of a plurality of semiconductor layers provided in a wafer; determining a within-wafer distribution of etching amount for the at least one of the plurality of semiconductor layers based on the measured within-wafer distribution of the physical quantity; and etching the at least one of the plurality of semiconductor layers based on the determined within-wafer distribution of the etching amount so that the etching amount is locally varied within the wafer.

摘要翻译： 一种半导体器件的制造方法，包括： 测量物理量的晶片内分布; 并蚀刻晶片，使得物理量在晶片内接近恒定。 或者，制造半导体器件的方法包括：测量设置在晶片中的多个半导体层中的至少一个的物理量的晶片内分布; 基于所测量的所述物理量的晶片内分布，确定所述多个半导体层中的所述至少一个的蚀刻量的晶片内分布; 并且基于确定的蚀刻量的晶片内分布来蚀刻多个半导体层中的至少一个，使得蚀刻量在晶片内局部变化。