公开(公告)号：US06239464B1

公开(公告)日：2001-05-29

申请号：US09226720

申请日：1999-01-07

申请人： Masanobu Tsuchitani ,  Keita Suzuki ,  Akihiko Osawa ,  Yoshiro Baba

发明人： Masanobu Tsuchitani ,  Keita Suzuki ,  Akihiko Osawa ,  Yoshiro Baba

IPC分类号： H01L29792

CPC分类号： H01L29/66666 ,  H01L29/42368 ,  H01L29/4238

摘要： A semiconductor device, which can have a uniform film on open ends of trenches by using materials having a different oxidation rate, and a fabrication method thereof are provided. The semiconductor device having trenches configured to have open ends covered with an oxidation film made of a material having an oxidation rate faster than that of a semiconductor substrate and a fabrication method thereof are provided.

摘要翻译： 提供一种半导体器件及其制造方法，该半导体器件可以通过使用具有不同氧化速率的材料在沟槽的开口端上具有均匀的膜。 具有沟槽的半导体器件被配置为具有用氧化速率快于半导体衬底的材料制成的氧化膜覆盖的开口端及其制造方法。

公开(公告)号：US6060747A

公开(公告)日：2000-05-09

申请号：US159122

申请日：1998-09-23

申请人： Hideki Okumura ,  Akihiko Osawa ,  Yoshiro Baba ,  Noboru Matsuda ,  Masanobu Tsuchitani

发明人： Hideki Okumura ,  Akihiko Osawa ,  Yoshiro Baba ,  Noboru Matsuda ,  Masanobu Tsuchitani

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/739

CPC分类号： H01L29/0696

摘要： A semiconductor device is characterized in that source electrode contact regions, each of which is formed of a first conductivity type source layer and a second conductivity type base layer in a surface of a semiconductor surface, are formed at respective intersectional points of a diagonally-arranged lattice, and in that a trench having a gate electrode buried therein is formed so as to snake through the contact regions alternately. By virtue of the structure, the trench arrangement and source/base simultaneous contact quality are improved, to thereby increase a trench density (channel density) per unit area.

摘要翻译： 半导体器件的特征在于，在对角线布置的各个交点处形成源极电极接触区域，每个源极电极接触区域由半导体表面的第一导电型源极层和第二导电型基极层形成， 并且具有埋入其中的具有栅电极的沟槽形成为交替地穿过接触区域。 通过该结构，提高了沟槽布置和源极/基极同时接触质量，从而增加了每单位面积的沟槽密度（沟道密度）。

公开(公告)号：US5578508A

公开(公告)日：1996-11-26

申请号：US426233

申请日：1995-04-21

申请人： Yoshiro Baba ,  Satoshi Yanagiya ,  Noboru Matsuda ,  Akihiko Osawa ,  Masanobu Tsuchitani

发明人： Yoshiro Baba ,  Satoshi Yanagiya ,  Noboru Matsuda ,  Akihiko Osawa ,  Masanobu Tsuchitani

IPC分类号： H01L21/302 ,  H01L21/265 ,  H01L21/266 ,  H01L21/306 ,  H01L21/336 ,  H01L29/78 ,  H01L21/304 ,  H01L21/76

CPC分类号： H01L29/7813 ,  H01L29/66734 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/7838

摘要： A channel region and a source region are formed on a surface of a substrate by double diffusion. A trench is formed so as to penetrate a part of the channel region and a part of the source region and reach the substrate. After an insulating film is formed on an inner wall of the trench, a polysilicon layer is buried up to an intermediate portion of the trench. In this state, channel ions are implanted in a side surface region of the trench, thereby depleting a channel region. Thereafter, a polysilicon layer for leading out a gate is buried in the trench.

摘要翻译： 通过双扩散在衬底的表面上形成沟道区域和源极区域。 形成沟槽，以便穿透沟道区域的一部分和源区域的一部分并到达衬底。 在沟槽的内壁上形成绝缘膜之后，将多晶硅层埋入沟槽的中间部分。 在这种状态下，沟道离子注入沟槽的侧表面区域，从而耗尽沟道区域。 此后，用于引出栅极的多晶硅层被埋在沟槽中。

公开(公告)号：US6031276A

公开(公告)日：2000-02-29

申请号：US950841

申请日：1997-10-15

申请人： Akihiko Osawa ,  Yoshiro Baba ,  Masanobu Tsuchitani ,  Shizue Hori

发明人： Akihiko Osawa ,  Yoshiro Baba ,  Masanobu Tsuchitani ,  Shizue Hori

IPC分类号： H01L29/74 ,  H01L21/265 ,  H01L21/266 ,  H01L21/322 ,  H01L21/329 ,  H01L29/32 ,  H01L29/861 ,  H01L26/30

CPC分类号： H01L29/66136 ,  H01L21/26506 ,  H01L21/266 ,  H01L29/32

摘要： A semiconductor device includes a plurality of defect layers separated from one another in the semiconductor layer. A distance separating any adjacent ones of the defect layers is kept such that they are prevented from contacting each other and those regions having effect of shortening a carrier lifetime overlap each other.

摘要翻译： 半导体器件包括在半导体层中彼此分离的多个缺陷层。 保持分离任何相邻的缺陷层的距离使得它们被防止彼此接触，并且那些具有缩短载流子寿命的作用的那些区域彼此重叠。

公开(公告)号：US06337498B1

公开(公告)日：2002-01-08

申请号：US09249296

申请日：1999-02-12

申请人： Shigeru Hasegawa ,  Hideo Matsuda ,  Yoshiro Baba ,  Masanobu Tsuchitani

发明人： Shigeru Hasegawa ,  Hideo Matsuda ,  Yoshiro Baba ,  Masanobu Tsuchitani

IPC分类号： H01L2994

CPC分类号： H01L29/7397 ,  H01L29/0696 ,  H01L29/4238

摘要： A semiconductor device such as an IGBT having trench gates in a form of stripes, and manufacturing method, wherein concentration of stresses in only a single direction is relieved and the generation of a leakage current and crystal defects in the IGBT is prevented. In one embodiment, the inside of a terminal area of an IGBT is divided into a single gate pad area and plural element areas by a wiring area. The respective element areas are arranged in such a manner that the directions of trench gates formed in the respective element areas cross at right angles with respect to the directions of trench gates of respective adjacent element areas.

摘要翻译： 诸如具有条形沟槽栅极的IGBT的半导体器件以及其中单个方向上的应力集中被释放并且防止了IGBT中产生漏电流和晶体缺陷的制造方法。 在一个实施例中，IGBT的端子区域的内部通过布线区域分成单个栅极焊盘区域和多个元件区域。 相应的元件区域被布置成使得形成在各个元件区域中的沟槽栅极的方向相对于各个相邻元件区域的沟槽栅极的方向成直角交叉。

公开(公告)号：US5770514A

公开(公告)日：1998-06-23

申请号：US787573

申请日：1997-01-22

申请人： Noboru Matsuda ,  Yoshiro Baba ,  Satoshi Yanagiya ,  Masanobu Tsuchitani

发明人： Noboru Matsuda ,  Yoshiro Baba ,  Satoshi Yanagiya ,  Masanobu Tsuchitani

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/423 ,  H01L29/739 ,  H01L29/772 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/7397 ,  H01L29/7813 ,  H01L29/4232 ,  H01L29/4238

摘要： In a vertical field effect transistor having a trench gate and a method of manufacturing the same according to the present invention, p-type base and n.sup.+ -type source diffusion layers are formed in this order in a surface region of an n.sup.31 -type epitaxial layer on an n.sup.+ -type semiconductor substrate. A trench is then provided to such a depth as to penetrate the diffusion layers. A dope polysilicon layer is deposited and buried into the trench with a gate insulation film interposed between them. The polysilicon layer is etched to have the same level as that of the entrance of the trench, and a dope polysilicon layer 18 is selectively grown thereon, thereby forming a trench gate in which an upper corner portion of the trench is not covered with a gate electrode. Consequently, the concentration of electric fields at the corner portion can be mitigated thereby to increase an absolute withstand voltage of the gate and the variations in threshold voltage can be suppressed in a BT test.

摘要翻译： 在根据本发明的具有沟槽栅的垂直场效应晶体管及其制造方法中，在n31型外延层的表面区域中依次形成p型基极和n +型源极扩散层 在n +型半导体衬底上。 然后将沟槽提供到穿透扩散层的深度。 将掺杂多晶硅层沉积并埋入沟槽中，并在其间插入栅极绝缘膜。 蚀刻多晶硅层以与沟槽的入口具有相同的电平，并且在其上选择性地生长掺杂多晶硅层18，从而形成沟槽栅极，其中沟槽的上角部分未被栅极覆盖 电极。 因此，可以减轻角部处的电场的集中，从而提高栅极的绝对耐受电压，并且可以在BT测试中抑制阈值电压的变化。

公开(公告)号：US6010950A

公开(公告)日：2000-01-04

申请号：US026508

申请日：1998-02-19

申请人： Hideki Okumura ,  Akihiko Osawa ,  Yoshiro Baba

发明人： Hideki Okumura ,  Akihiko Osawa ,  Yoshiro Baba

IPC分类号： H01L21/02 ,  H01L21/18 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L21/30

CPC分类号： H01L21/18 ,  H01L21/762 ,  H01L21/76202 ,  H01L21/76251 ,  H01L21/76264

摘要： The most distinctive feature of the present invention lies in that a warp and crystal defects can be prevented from occurring and a processing margin for forming an isolation groove can be improved in an intelligent power device including a power element section and an IC control section within one chip. A bonded wafer is obtained by bonding an active-layer substrate and a supporting substrate with an epitaxially grown silicon layer interposed therebetween so as to cover an oxide film selectively formed at the interface of the active-layer substrate. Isolation trenches are then formed in the bonded wafer to such a depth as to reach the oxide film from the element forming surface of the active-layer substrate. Thus, an IC controller is formed within a dielectric isolation region surrounded with the isolation trenches and the oxide film and accordingly the IC controller can effectively be isolated by a dielectric.

摘要翻译： 本发明的最显着的特征在于，可以防止发生翘曲和晶体缺陷，并且可以在包括功率元件部分和IC控制部分的智能功率器件的一个智能功率器件内改善用于形成隔离沟槽的加工余量 芯片。 通过将有源层衬底和支撑衬底与外延生长的硅层接合以便覆盖在有源层衬底的界面处有选择地形成的氧化物膜而获得接合晶片。 然后在接合的晶片中形成隔离沟槽到从活性层衬底的元件形成表面到达氧化物膜的深度。 因此，在由隔离沟槽和氧化物膜包围的电介质隔离区域内形成IC控制器，因此可以通过电介质来有效地隔离IC控制器。

公开(公告)号：US4984052A

公开(公告)日：1991-01-08

申请号：US418587

申请日：1989-10-10

申请人： Yutaka Koshino ,  Yoshiro Baba ,  Akihiko Osawa ,  Satoshi Yanagiya

发明人： Yutaka Koshino ,  Yoshiro Baba ,  Akihiko Osawa ,  Satoshi Yanagiya

IPC分类号： H01L21/02 ,  H01L21/762 ,  H01L21/763 ,  H01L27/12

CPC分类号： H01L21/763 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76281 ,  H01L21/76286 ,  Y10S257/914

摘要： A bonded substrate comprises a first semiconductor substrate in which a plurality of semiconductor elements are formed, a second semiconductor substrate adhered to the first semiconductor substrate so as to support it by means of an insulating layer interposed therebetween, a first semi-insulating polysilicon layer interposed between the first semiconductor substrate and the insulating layer, and a second semi-insulating polysilicon layer interposed between the insulating layer and the second semiconductor substrate. The semi-insulating polysilicon layers serve to reduce the voltage applied to the insulating layer and to prevent the insulating layer from being etched.

摘要翻译： 键合衬底包括其中形成有多个半导体元件的第一半导体衬底，第二半导体衬底，其粘附到第一半导体衬底，以便通过插入其间的绝缘层来支撑它;第一半绝缘多晶硅层， 在第一半导体衬底和绝缘层之间，以及插入在绝缘层和第二半导体衬底之间的第二半绝缘多晶硅层。 半绝缘多晶硅层用于降低施加到绝缘层的电压并防止绝缘层被蚀刻。

公开(公告)号：US5731637A

公开(公告)日：1998-03-24

申请号：US687032

申请日：1996-07-25

申请人： Shizue Hori ,  Akihiko Osawa ,  Yoshiro Baba ,  Shigeo Yawata

发明人： Shizue Hori ,  Akihiko Osawa ,  Yoshiro Baba ,  Shigeo Yawata

IPC分类号： H01L29/74 ,  H01L21/265 ,  H01L21/322 ,  H01L21/332 ,  H01L29/08 ,  H01L23/58

CPC分类号： H01L29/66363 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/3221 ,  H01L29/083

摘要： The object of the present invention is to provide a method of manufacturing high-performance, high-breakdown-voltage semiconductor devices which suppresses an increase in the junction leakage current due to heavy metal contamination without increasing the number of manufacturing steps. A method of manufacturing semiconductor devices according to the invention, comprises the steps of ion-implanting one or more elements selected from a group of silicon, carbon, nitrogen, oxygen, hydrogen, argon, helium, and xenon into at least one surface of a semiconductor substrate of a first conductivity type at a dose of 1.times.10.sup.15 cm.sup.-2 or more to form a distortion layer, oxidizing the surface of the substrate to form an oxide film, ion-implanting impurities of a second conductivity type at a low concentration (a dose of less than 1.times.10.sup.15 cm.sup.-2) via the oxide film into the one surface of the substrate, ion-implanting impurities of the second conductivity type at a high concentration (a dose of 1.times.10.sup.15 cm.sup.-2 or more) via the oxide film into the other surface of the substrate, and forming a junction by heat treatment.

摘要翻译： 本发明的目的是提供一种制造高性能，高耐击穿电压半导体器件的方法，其抑制由于重金属污染导致的结漏电流的增加，而不增加制造步骤的数量。 根据本发明的制造半导体器件的方法包括以下步骤：将选自硅，碳，氮，氧，氢，氩，氦和氙的一种或多种元素离子注入至 以1×10 15 cm -2以上的剂量的第一导电类型的半导体衬底形成失真层，氧化衬底的表面以形成氧化膜，以低浓度离子注入第二导电类型的杂质（a 通过该氧化膜将该剂量小于1×10 15 cm -2）通过氧化膜以高浓度（1×10 15 cm -2以上的剂量）将第二导电型的杂质离子注入到 衬底的另一个表面，并通过热处理形成结。

公开(公告)号：US5554872A

公开(公告)日：1996-09-10

申请号：US412215

申请日：1995-03-27

申请人： Yoshiro Baba ,  Shunichi Hiraki ,  Akihiko Osawa

发明人： Yoshiro Baba ,  Shunichi Hiraki ,  Akihiko Osawa

IPC分类号： H01L21/762 ,  H01L27/02 ,  H01L27/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/861 ,  H01L29/76

CPC分类号： H01L29/7824 ,  H01L27/0218 ,  H01L29/1087 ,  Y10S257/901

摘要： In a semiconductor device including a composite substrate formed by bonding first and second semiconductor substrates to each other through an oxide film and an insulator isolation trench formed from a major surface of the first semiconductor substrate to reach the oxide film and to surround an element forming region, when the potential of the second substrate is set at a potential higher than the minimum potential in the element forming region of the first substrate, an breakdown voltage can be increased. In a semiconductor integrated circuit having an element isolation region, a semiconductor device of a perfect dielectric isolation structure having an element forming region having a thickness smaller than that of the element forming region of a P-N junction isolation structure is used to reduce, e.g., a base curvature influence, thereby obtaining a further high breakdown voltage.

摘要翻译： 在包括通过氧化膜将第一和第二半导体衬底彼此接合而形成的复合衬底的半导体器件和由第一半导体衬底的主表面形成的绝缘体隔离沟槽到达氧化膜并且围绕元件形成区域 当第二基板的电位设定为高于第一基板的元件形成区域中的最小电位的电位时，可以提高击穿电压。 在具有元件隔离区域的半导体集成电路中，使用具有比PN结隔离结构的元件形成区域的厚度小的元件形成区域的完美电介质隔离结构的半导体器件，以减少例如 基础曲率影响，从而获得更高的击穿电压。