公开(公告)号：US6031276A

公开(公告)日：2000-02-29

申请号：US950841

申请日：1997-10-15

申请人： Akihiko Osawa ,  Yoshiro Baba ,  Masanobu Tsuchitani ,  Shizue Hori

发明人： Akihiko Osawa ,  Yoshiro Baba ,  Masanobu Tsuchitani ,  Shizue Hori

IPC分类号： H01L29/74 ,  H01L21/265 ,  H01L21/266 ,  H01L21/322 ,  H01L21/329 ,  H01L29/32 ,  H01L29/861 ,  H01L26/30

CPC分类号： H01L29/66136 ,  H01L21/26506 ,  H01L21/266 ,  H01L29/32

摘要： A semiconductor device includes a plurality of defect layers separated from one another in the semiconductor layer. A distance separating any adjacent ones of the defect layers is kept such that they are prevented from contacting each other and those regions having effect of shortening a carrier lifetime overlap each other.

摘要翻译： 半导体器件包括在半导体层中彼此分离的多个缺陷层。 保持分离任何相邻的缺陷层的距离使得它们被防止彼此接触，并且那些具有缩短载流子寿命的作用的那些区域彼此重叠。

公开(公告)号：US6084263A

公开(公告)日：2000-07-04

申请号：US27727

申请日：1998-02-23

申请人： Masanobu Tsuchitani ,  Shizue Hori ,  Akihiko Osawa

发明人： Masanobu Tsuchitani ,  Shizue Hori ,  Akihiko Osawa

IPC分类号： H01L29/861 ,  H01L29/06 ,  H01L29/739 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7395 ,  H01L29/0611

摘要： The main characteristic feature of the invention is to prevent a leakage current from flowing when a planar type semiconductor device having a high breakdown voltage is reverse-biased. For example, a semiconductive film is formed on the surface of an n-type Si substrate between a second p-type base layer selectively formed on the surface of the Si substrate and a channel stop layer formed to surround the second p-type base layer at a predetermined interval. The dangling bond density of the semiconductive film is set at 1.25.times.1018 cm.sup.-3. With this structure, the discrete level in the band gap approach a continuum, and the time required to populate the trapping level in the semiconductive film with carriers is shortened.

摘要翻译： 本发明的主要特征是当具有高击穿电压的平面型半导体器件被反向偏置时，防止漏电流流动。 例如，在n型Si衬底的表面上形成半导体膜，该第二p型基极层选择性地形成在Si衬底表面上的第二p型基极层和形成为围绕第二p型基极层的沟道阻挡层 以预定间隔。 半导体膜的悬挂键密度设定为1.25×10 18 cm -3。 利用这种结构，带隙中的离散水平接近连续体，缩短了用载体填充半导体薄膜中的捕获水平所需的时间。

公开(公告)号：US5731637A

公开(公告)日：1998-03-24

申请号：US687032

申请日：1996-07-25

申请人： Shizue Hori ,  Akihiko Osawa ,  Yoshiro Baba ,  Shigeo Yawata

发明人： Shizue Hori ,  Akihiko Osawa ,  Yoshiro Baba ,  Shigeo Yawata

IPC分类号： H01L29/74 ,  H01L21/265 ,  H01L21/322 ,  H01L21/332 ,  H01L29/08 ,  H01L23/58

CPC分类号： H01L29/66363 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/3221 ,  H01L29/083

摘要： The object of the present invention is to provide a method of manufacturing high-performance, high-breakdown-voltage semiconductor devices which suppresses an increase in the junction leakage current due to heavy metal contamination without increasing the number of manufacturing steps. A method of manufacturing semiconductor devices according to the invention, comprises the steps of ion-implanting one or more elements selected from a group of silicon, carbon, nitrogen, oxygen, hydrogen, argon, helium, and xenon into at least one surface of a semiconductor substrate of a first conductivity type at a dose of 1.times.10.sup.15 cm.sup.-2 or more to form a distortion layer, oxidizing the surface of the substrate to form an oxide film, ion-implanting impurities of a second conductivity type at a low concentration (a dose of less than 1.times.10.sup.15 cm.sup.-2) via the oxide film into the one surface of the substrate, ion-implanting impurities of the second conductivity type at a high concentration (a dose of 1.times.10.sup.15 cm.sup.-2 or more) via the oxide film into the other surface of the substrate, and forming a junction by heat treatment.

摘要翻译： 本发明的目的是提供一种制造高性能，高耐击穿电压半导体器件的方法，其抑制由于重金属污染导致的结漏电流的增加，而不增加制造步骤的数量。 根据本发明的制造半导体器件的方法包括以下步骤：将选自硅，碳，氮，氧，氢，氩，氦和氙的一种或多种元素离子注入至 以1×10 15 cm -2以上的剂量的第一导电类型的半导体衬底形成失真层，氧化衬底的表面以形成氧化膜，以低浓度离子注入第二导电类型的杂质（a 通过该氧化膜将该剂量小于1×10 15 cm -2）通过氧化膜以高浓度（1×10 15 cm -2以上的剂量）将第二导电型的杂质离子注入到 衬底的另一个表面，并通过热处理形成结。

公开(公告)号：US06239464B1

公开(公告)日：2001-05-29

申请号：US09226720

申请日：1999-01-07

申请人： Masanobu Tsuchitani ,  Keita Suzuki ,  Akihiko Osawa ,  Yoshiro Baba

发明人： Masanobu Tsuchitani ,  Keita Suzuki ,  Akihiko Osawa ,  Yoshiro Baba

IPC分类号： H01L29792

CPC分类号： H01L29/66666 ,  H01L29/42368 ,  H01L29/4238

摘要： A semiconductor device, which can have a uniform film on open ends of trenches by using materials having a different oxidation rate, and a fabrication method thereof are provided. The semiconductor device having trenches configured to have open ends covered with an oxidation film made of a material having an oxidation rate faster than that of a semiconductor substrate and a fabrication method thereof are provided.

摘要翻译： 提供一种半导体器件及其制造方法，该半导体器件可以通过使用具有不同氧化速率的材料在沟槽的开口端上具有均匀的膜。 具有沟槽的半导体器件被配置为具有用氧化速率快于半导体衬底的材料制成的氧化膜覆盖的开口端及其制造方法。

公开(公告)号：US6060747A

公开(公告)日：2000-05-09

申请号：US159122

申请日：1998-09-23

申请人： Hideki Okumura ,  Akihiko Osawa ,  Yoshiro Baba ,  Noboru Matsuda ,  Masanobu Tsuchitani

发明人： Hideki Okumura ,  Akihiko Osawa ,  Yoshiro Baba ,  Noboru Matsuda ,  Masanobu Tsuchitani

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/739

CPC分类号： H01L29/0696

摘要： A semiconductor device is characterized in that source electrode contact regions, each of which is formed of a first conductivity type source layer and a second conductivity type base layer in a surface of a semiconductor surface, are formed at respective intersectional points of a diagonally-arranged lattice, and in that a trench having a gate electrode buried therein is formed so as to snake through the contact regions alternately. By virtue of the structure, the trench arrangement and source/base simultaneous contact quality are improved, to thereby increase a trench density (channel density) per unit area.

摘要翻译： 半导体器件的特征在于，在对角线布置的各个交点处形成源极电极接触区域，每个源极电极接触区域由半导体表面的第一导电型源极层和第二导电型基极层形成， 并且具有埋入其中的具有栅电极的沟槽形成为交替地穿过接触区域。 通过该结构，提高了沟槽布置和源极/基极同时接触质量，从而增加了每单位面积的沟槽密度（沟道密度）。

公开(公告)号：US5578508A

公开(公告)日：1996-11-26

申请号：US426233

申请日：1995-04-21

申请人： Yoshiro Baba ,  Satoshi Yanagiya ,  Noboru Matsuda ,  Akihiko Osawa ,  Masanobu Tsuchitani

发明人： Yoshiro Baba ,  Satoshi Yanagiya ,  Noboru Matsuda ,  Akihiko Osawa ,  Masanobu Tsuchitani

IPC分类号： H01L21/302 ,  H01L21/265 ,  H01L21/266 ,  H01L21/306 ,  H01L21/336 ,  H01L29/78 ,  H01L21/304 ,  H01L21/76

CPC分类号： H01L29/7813 ,  H01L29/66734 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/7838

摘要： A channel region and a source region are formed on a surface of a substrate by double diffusion. A trench is formed so as to penetrate a part of the channel region and a part of the source region and reach the substrate. After an insulating film is formed on an inner wall of the trench, a polysilicon layer is buried up to an intermediate portion of the trench. In this state, channel ions are implanted in a side surface region of the trench, thereby depleting a channel region. Thereafter, a polysilicon layer for leading out a gate is buried in the trench.

摘要翻译： 通过双扩散在衬底的表面上形成沟道区域和源极区域。 形成沟槽，以便穿透沟道区域的一部分和源区域的一部分并到达衬底。 在沟槽的内壁上形成绝缘膜之后，将多晶硅层埋入沟槽的中间部分。 在这种状态下，沟道离子注入沟槽的侧表面区域，从而耗尽沟道区域。 此后，用于引出栅极的多晶硅层被埋在沟槽中。

公开(公告)号：US20060145290A1

公开(公告)日：2006-07-06

申请号：US11294411

申请日：2005-12-06

申请人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Akihiko Osawa ,  Wataru Saito ,  Masakazu Yamaguchi ,  Ichiro Omura

发明人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Akihiko Osawa ,  Wataru Saito ,  Masakazu Yamaguchi ,  Ichiro Omura

IPC分类号： H01L29/00 ,  H01L21/425 ,  H01L21/336

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/7802

摘要： A semiconductor device includes a diffusion area formed in a semiconductor layer of a first conductive type. The diffusion area comprises first and second impurity diffusion areas of the first and second conductive types, respectively. The diffusion area has a first and second areas which are defined by an impurity concentration of the first and second impurity diffusion areas. A junction between the first and second area is formed in a portion in which the first and second impurity diffusion areas overlap each other. A period of the impurity concentration, in a planar direction of the semiconductor layer, of the first or second area is smaller than the maximum width, in the planar direction of the semiconductor layer, of the first and second impurity diffusion areas constituting the first or second area.

公开(公告)号：US06995426B2

公开(公告)日：2006-02-07

申请号：US10327937

申请日：2002-12-26

申请人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Akihiko Osawa ,  Wataru Saito ,  Masakazu Yamaguchi ,  Ichiro Omura

发明人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Akihiko Osawa ,  Wataru Saito ,  Masakazu Yamaguchi ,  Ichiro Omura

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/7802

摘要： A semiconductor device includes a diffusion area formed in a semiconductor layer of a first conductive type. The diffusion area comprises first and second impurity diffusion areas of the first and second conductive types, respectively. The diffusion area has a first and second areas which are defined by an impurity concentration of the first and second impurity diffusion areas. A junction between the first and second area is formed in a portion in which the first and second impurity diffusion areas overlap each other. A period of the impurity concentration, in a planar direction of the semiconductor layer, of the first or second area is smaller than the maximum width, in the planar direction of the semiconductor layer, of the first and second impurity diffusion areas constituting the first or second area.

摘要翻译： 半导体器件包括形成在第一导电类型的半导体层中的扩散区域。 扩散区域分别包括第一和第二导电类型的第一和第二杂质扩散区域。 扩散区域具有由第一和第二杂质扩散区域的杂质浓度限定的第一和第二区域。 第一和第二区域之间的结点形成在第一和第二杂质扩散区域彼此重叠的部分中。 在第一或第二区域的半导体层的平面方向上的杂质浓度的周期小于半导体层的平面方向上的构成第一或第二区域的第一和第二杂质扩散区域的最大宽度 第二区。

公开(公告)号：US6010950A

公开(公告)日：2000-01-04

申请号：US026508

申请日：1998-02-19

申请人： Hideki Okumura ,  Akihiko Osawa ,  Yoshiro Baba

发明人： Hideki Okumura ,  Akihiko Osawa ,  Yoshiro Baba

IPC分类号： H01L21/02 ,  H01L21/18 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L21/30

CPC分类号： H01L21/18 ,  H01L21/762 ,  H01L21/76202 ,  H01L21/76251 ,  H01L21/76264

摘要： The most distinctive feature of the present invention lies in that a warp and crystal defects can be prevented from occurring and a processing margin for forming an isolation groove can be improved in an intelligent power device including a power element section and an IC control section within one chip. A bonded wafer is obtained by bonding an active-layer substrate and a supporting substrate with an epitaxially grown silicon layer interposed therebetween so as to cover an oxide film selectively formed at the interface of the active-layer substrate. Isolation trenches are then formed in the bonded wafer to such a depth as to reach the oxide film from the element forming surface of the active-layer substrate. Thus, an IC controller is formed within a dielectric isolation region surrounded with the isolation trenches and the oxide film and accordingly the IC controller can effectively be isolated by a dielectric.

摘要翻译： 本发明的最显着的特征在于，可以防止发生翘曲和晶体缺陷，并且可以在包括功率元件部分和IC控制部分的智能功率器件的一个智能功率器件内改善用于形成隔离沟槽的加工余量 芯片。 通过将有源层衬底和支撑衬底与外延生长的硅层接合以便覆盖在有源层衬底的界面处有选择地形成的氧化物膜而获得接合晶片。 然后在接合的晶片中形成隔离沟槽到从活性层衬底的元件形成表面到达氧化物膜的深度。 因此，在由隔离沟槽和氧化物膜包围的电介质隔离区域内形成IC控制器，因此可以通过电介质来有效地隔离IC控制器。

公开(公告)号：US4984052A

公开(公告)日：1991-01-08

申请号：US418587

申请日：1989-10-10

申请人： Yutaka Koshino ,  Yoshiro Baba ,  Akihiko Osawa ,  Satoshi Yanagiya

发明人： Yutaka Koshino ,  Yoshiro Baba ,  Akihiko Osawa ,  Satoshi Yanagiya

IPC分类号： H01L21/02 ,  H01L21/762 ,  H01L21/763 ,  H01L27/12

CPC分类号： H01L21/763 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76281 ,  H01L21/76286 ,  Y10S257/914

摘要： A bonded substrate comprises a first semiconductor substrate in which a plurality of semiconductor elements are formed, a second semiconductor substrate adhered to the first semiconductor substrate so as to support it by means of an insulating layer interposed therebetween, a first semi-insulating polysilicon layer interposed between the first semiconductor substrate and the insulating layer, and a second semi-insulating polysilicon layer interposed between the insulating layer and the second semiconductor substrate. The semi-insulating polysilicon layers serve to reduce the voltage applied to the insulating layer and to prevent the insulating layer from being etched.

摘要翻译： 键合衬底包括其中形成有多个半导体元件的第一半导体衬底，第二半导体衬底，其粘附到第一半导体衬底，以便通过插入其间的绝缘层来支撑它;第一半绝缘多晶硅层， 在第一半导体衬底和绝缘层之间，以及插入在绝缘层和第二半导体衬底之间的第二半绝缘多晶硅层。 半绝缘多晶硅层用于降低施加到绝缘层的电压并防止绝缘层被蚀刻。