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21 条记录 (耗时 0.016 秒)

    Semiconductor device comprising a salicide structure
    1.
    发明授权
    Semiconductor device comprising a salicide structure 失效
    包括硅化物结构的半导体器件

    公开(公告)号：US5635746A

    公开(公告)日：1997-06-03

    申请号：US575194

    申请日：1995-12-20

    申请人： Masatoshi Kimura ,  Masao Sugiyama

    发明人： Masatoshi Kimura ,  Masao Sugiyama

    IPC分类号： H01L29/78 ,  H01L21/285 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/76

    CPC分类号： H01L29/6659 ,  H01L21/28518 ,  H01L21/823443 ,  H01L21/823835 ,  Y10S257/914

    摘要： After formation a gate electrode and source/drain regions, N ions or O ions are implanted into a predetermined region using a resist mask, and a Ti layer is deposited on the entire face of a substrate, and then the Ti layer is silicided in self-alignment by a heat treatment, whereby a high resistivity TixNySiz mixing layer is formed the predetermined region on the gate electrode and the source/drain regions 10, and a low resistivity TiSi.sub.2 layer 12 is formed on another region.

    摘要翻译： 在形成栅电极和源/漏区之后，使用抗蚀剂掩模将N离子或O离子注入到预定区域中，并且在衬底的整个表面上沉积Ti层，然后Ti层自身被硅化 通过热处理对准，由此在栅极电极和源极/漏极区域10上形成预定区域的高电阻率TixNySiz混合层，并且在另一个区域上形成低电阻率TiSi 2层12。

    Method of manufacturing a semiconductor device employing salicide technology
    2.
    发明授权
    Method of manufacturing a semiconductor device employing salicide technology 失效
    制造使用自对准硅化物技术的半导体器件的方法

    公开(公告)号：US5956617A

    公开(公告)日：1999-09-21

    申请号：US816183

    申请日：1997-03-12

    申请人： Masatoshi Kimura ,  Masao Sugiyama

    发明人： Masatoshi Kimura ,  Masao Sugiyama

    IPC分类号： H01L29/78 ,  H01L21/285 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/44

    CPC分类号： H01L29/6659 ,  H01L21/28518 ,  H01L21/823443 ,  H01L21/823835 ,  Y10S257/914

    摘要： After formation of a gate electrode and source/drain regions, N ions or O ions are implanted into a predetermined region using a resist mask, and a Ti layer is deposited on the entire face of a substrate. The Ti layer is then silicided in self-alignment by a heat treatment, whereby a high resistivity TixNySiz mixing layer is formed the predetermined region on the gate electrode and the source/drain regions 10, and a low resistivity TiSi.sub.2 layer 12 is formed on another region.

    摘要翻译： 在形成栅电极和源极/漏极区之后，使用抗蚀剂掩模将N离子或O离子注入到预定区域中，并且在衬底的整个表面上沉积Ti层。 然后通过热处理使Ti层自对准，由此在栅极电极和源极/漏极区域10上形成预定区域的高电阻率TixNySiz混合层，并且在另一个上形成低电阻率TiSi 2层12 地区。

    Method of manufacturing semiconductor device
    4.
    发明授权
    Method of manufacturing semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US06461946B2

    公开(公告)日：2002-10-08

    申请号：US09843859

    申请日：2001-04-30

    申请人： Takeshi Kitani ,  Katsumi Eikyu ,  Masao Sugiyama

    发明人： Takeshi Kitani ,  Katsumi Eikyu ,  Masao Sugiyama

    IPC分类号： H01L2104

    CPC分类号： H01L21/26513 ,  H01L21/26586 ,  H01L21/76218 ,  H01L21/76237 ,  H01L21/823878 ,  H01L21/823892

    摘要： Both P type and N type impurities are implanted from a plurality of directions. The tilt angle &thgr; of the implantation direction against the normal of the main surface of a semiconductor substrate is fixed to 10°, and the deflection angle &phgr; is set to such four directions (X, X+90°, X+180°, and X+270°, where X is an arbitrary angle) that projecting components of a vector indicating the implantation direction are opposed to each other on two lines that cross each other at right angles along the main surface of the semiconductor substrate. Thereby, the dependency of the breakdown voltage of element isolation on the direction of a well boundary is suppressed to realize a high breakdown voltage of element isolation in all directions.

    摘要翻译： 从多个方向注入P型和N型杂质。 将注入方向相对于半导体衬底的主表面的法线的倾斜角度θ固定为10°，将偏转角度phi设定为这样的四个方向（X，X + 90°，X + 180°， 在沿着半导体基板的主表面成直角交叉的两条线上投影指示注入方向的矢量的分量相对的X + 270°，其中X是任意角度）。 因此，抑制元件隔离的击穿电压对阱边界的方向的依赖性，以实现元件隔离在所有方向上的高击穿电压。

    Semiconductor device comprising layered positional detection marks and manufacturing method thereof
    6.
    发明授权
    Semiconductor device comprising layered positional detection marks and manufacturing method thereof 失效
    包括分层位置检测标记的半导体器件及其制造方法

    公开(公告)号：US06723614B2

    公开(公告)日：2004-04-20

    申请号：US10003307

    申请日：2001-12-06

    申请人： Masao Sugiyama

    发明人： Masao Sugiyama

    IPC分类号： H01L2176

    CPC分类号： H01L23/544 ,  G03F9/7084 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

    摘要： A semiconductor device that permits effective use of a region positioned under a positional detection mark or an external electrode, i.e., the region that has not been conventionally utilized may be provided. In a semiconductor device including a lower layer, a shielding film and an upper layer, the lower layer includes at least one selected from the group consisting of a positional detection mark, a quality testing element, and a circuit element. The shielding film is formed on the lower layer and shields an energy beam used for detecting a positional detection mark. The upper layer includes a positional detection mark formed on the shielding film.

    摘要翻译： 可以提供允许有效利用位于位置检测标记或外部电极即未经常使用的区域的区域的半导体器件。 在包括下层，屏蔽膜和上层的半导体器件中，下层包括从由位置检测标记，质量检测元件和电路元件组成的组中选择的至少一种。 屏蔽膜形成在下层上并屏蔽用于检测位置检测标记的能量束。 上层包括形成在屏蔽膜上的位置检测标记。

    Semiconductor device having a dummy pattern
    7.
    发明授权
    Semiconductor device having a dummy pattern 失效
    具有虚拟图案的半导体器件

    公开(公告)号：US06486558B2

    公开(公告)日：2002-11-26

    申请号：US09767134

    申请日：2001-01-23

    申请人： Masao Sugiyama ,  Kenji Yoshiyama

    发明人： Masao Sugiyama ,  Kenji Yoshiyama

    IPC分类号： H01L2348

    CPC分类号： H01L23/522 ,  H01L21/823892 ,  H01L27/105 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device having a memory cell region comprising a plurality of memory cells is described, and a stable characteristic is imparted to all the memory cells provided in the memory cell block. Impurities are implanted into a memory cell region of a silicon substrate at predetermined intervals, thus forming a plurality of wells. A resist film used as a mask for implanting impurities has strip-shaped patterns and a broad pattern. Since the strip-shaped patterns located close to the broad pattern are inclined, the characteristics of the wells located in the vicinity of the outer periphery of the memory cell region become unstable. The wells having unstable characteristics are taken as dummy wells which do not affect the function of a semiconductor device.

    摘要翻译： 描述具有包括多个存储单元的存储单元区域的半导体器件，并且向设置在存储单元块中的所有存储单元赋予稳定特性。 杂质以预定间隔注入到硅衬底的存储单元区域中，从而形成多个阱。 用作植入杂质的掩模的抗蚀剂膜具有带状图案和宽图案。 由于位于靠近宽图案的带状图案倾斜，所以位于存储单元区域的外周附近的孔的特性变得不稳定。 将不稳定特性的阱作为不影响半导体器件功能的虚拟阱。

    SEMICONDUCTOR DEVICE
    8.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20110024847A1

    公开(公告)日：2011-02-03

    申请号：US12901858

    申请日：2010-10-11

    申请人： NAOZUMI MORINO ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

    发明人： NAOZUMI MORINO ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

    IPC分类号： H01L27/092

    CPC分类号： H01L21/823892 ,  H01L27/0629 ,  H01L27/0928 ,  H01L2224/05554

    摘要： There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

    摘要翻译： 提供了一种在具有三重阱结构的半导体器件中提高制造产量和产品可靠性的技术。 在形成深n型阱，浅P型阱和浅n型阱的p型衬底中，在与各个区域不同的区域中形成浅的p型阱。 形成在浅p型阱中的p型扩散抽头使用在第二层中的互连在深n型阱中连接到形成在浅n型阱中的p型扩散阱。 每个形成在深n型阱中的nMIS和pMIS的相应栅极电极使用在第二层或更高级层中的互连而在衬底中形成的nMIS和pMIS的相应漏电极耦合。

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE OF DUAL-GATE CONSTRUCTION, AND SEMICONDUCTOR DEVICE MANUFACTURED THEREBY INCLUDING FORMING A REGION OF OVER-LAPPING N-TYPE AND P-TYPE IMPURITIES WITH LOWER RESISTANCE
    10.
    发明授权
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE OF DUAL-GATE CONSTRUCTION, AND SEMICONDUCTOR DEVICE MANUFACTURED THEREBY INCLUDING FORMING A REGION OF OVER-LAPPING N-TYPE AND P-TYPE IMPURITIES WITH LOWER RESISTANCE 失效
    制造双门结构半导体器件的方法以及制造的半导体器件，其中包括形成具有较低电阻的N型和P型覆层的覆盖区域

    公开(公告)号：US06620666B2

    公开(公告)日：2003-09-16

    申请号：US09766844

    申请日：2001-01-23

    申请人： Kenji Yoshiyama ,  Keiichi Higashitani ,  Masao Sugiyama

    发明人： Kenji Yoshiyama ,  Keiichi Higashitani ,  Masao Sugiyama

    IPC分类号： H01L21337

    CPC分类号： H01L21/823842

    摘要： There is described a method of manufacturing a semiconductor device of dual-gate construction, which method prevents occurrence of a highly-resistant local area in a gate electrode of dual-gate construction. A polysilicon layer which is to become a conductive layer of a gate electrode of dual-gate construction is formed on an isolation oxide film. N-type impurities are implanted into an n-type implantation region of the polysilicon film while a photoresist film is taken as a mask. P-type impurities are implanted into a p-type impurity region of the polysilicon film 3 while another photoresist film is taken as a mask. Implantation of n-type impurities and implantation of p-type impurities are performed such that an overlapping area to be doped with these impurities in an overlapping manner is inevitably formed.

    摘要翻译： 描述了制造双栅极结构的半导体器件的方法，该方法防止在双栅极结构的栅电极中发生高电阻局部区域。 在隔离氧化膜上形成要成为双栅极结构的栅电极的导电层的多晶硅层。 将N型杂质注入到多晶硅膜的n型注入区域中，同时将光致抗蚀剂膜作为掩模。 将P型杂质注入多晶硅膜3的p型杂质区，同时将另一种光致抗蚀剂膜作为掩模。 进行n型杂质的注入和p型杂质的注入，使得不可避免地形成以这些重叠的方式掺杂这些杂质的重叠区域。