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公开(公告)号：US20150341000A1
公开(公告)日：2015-11-26
申请号：US14638212
申请日：2015-03-04
发明人： Ko KANAYA
IPC分类号： H03F1/32
CPC分类号： H03F1/3258 , H03F1/32 , H03F3/195 , H03F3/211 , H03F3/245 , H03F3/602 , H03F3/68 , H03F2200/387 , H03F2201/3215
摘要： A linearizer includes: a branch circuit having an input transmission line connected between an input terminal and a branch point, a first output transmission line connected between the branch point and a first output terminal, and a second output transmission line connected between the branch point and a second output terminal; a diode having an anode connected to the branch point and a cathode; and a bias circuit biasing the diode.
摘要翻译： 线性化装置包括：分支电路，其具有连接在输入端和分支点之间的输入传输线，连接在分支点和第一输出端之间的第一输出传输线，以及连接在分支点和 第二输出端子; 具有连接到分支点的阳极和阴极的二极管; 以及偏置二极管的偏置电路。
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公开(公告)号：US20240234338A1
公开(公告)日：2024-07-11
申请号：US18559516
申请日：2021-10-13
发明人： Tetsunari SAITO , Seiichi TSUJI , Hiroaki MINAMIDE , Ko KANAYA , Shunichi ABE
IPC分类号： H01L23/552 , H01L23/00 , H01L23/48 , H01L23/498
CPC分类号： H01L23/552 , H01L23/49827 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/49 , H01L23/481 , H01L2224/05553 , H01L2224/0557 , H01L2224/06152 , H01L2224/48091 , H01L2224/4813 , H01L2224/48157 , H01L2224/48245 , H01L2224/48476 , H01L2224/4911
摘要： An input feedthrough (8) and an output feedthrough (9) provided on the substrate (3) are wire-connected to an input pad (5) and an output pad (6) of the semiconductor chip (4) respectively. A metal seal ring (12) is provided on the substrate (3) is electrically connected to the metal plate (1) by a through-hole (15). A conductive cap (14) is bonded to the metal seal ring (12) and covers a place above the semiconductor chip (4). Both ends of an isolation metal wire (13) are electrically connected to the metal plate (1) and a loop comes into contact with a lower surface of the conductive cap (14). The isolation metal wire (13) constitutes an isolation wall partitioning an inner space into a region including the input feedthrough (8) and a region including the output feedthrough (9).
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公开(公告)号：US20240146262A1
公开(公告)日：2024-05-02
申请号：US18548214
申请日：2021-06-30
发明人： Ko KANAYA , Kazuya YAMAMOTO
CPC分类号： H03F3/245 , H01L23/66 , H03F1/56 , H03F3/195 , H01L2223/6611 , H01L2223/6655 , H03F2200/451
摘要： A power amplifier according to the present disclosure includes an input terminal that receives a high-frequency signal from an outside, an MMIC that receives the high-frequency signal via the input terminal and amplifies the high-frequency signal, an input matching circuit, a transistor that receives, via the input matching circuit, the high-frequency signal amplified by the MMIC and amplifies the high-frequency signal, an output matching circuit, an output terminal that receives a drain voltage of the transistor from the outside, receives, via the output matching circuit, the high-frequency signal amplified by the transistor, and outputs the high-frequency signal to the outside and a drain bias circuit board that connects a drain of the transistor and a drain of the MMIC, wherein the transistor and the MMIC are conjugately matched at impedance smaller than 50 Ω.
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公开(公告)号：US20180006152A1
公开(公告)日：2018-01-04
申请号：US15545373
申请日：2015-06-23
发明人： Shohei IMAI , Kazuhiro IYOMASA , Koji YAMANAKA , Hiroaki MAEHARA , Ko KANAYA , Tetsuo KUNII , Hideaki KATAYAMA
CPC分类号： H01L29/7831 , H01L21/822 , H01L23/66 , H01L27/04 , H01L27/0629 , H01L29/812 , H01L2223/6611 , H01L2223/6655 , H03F3/195 , H03F3/213 , H03F2200/12 , H03F2200/222 , H03F2200/451
摘要： A semiconductor device is provided with one or more gate fingers (20) that are provided in an active region on a semiconductor substrate (1), and a source finger (30) and a drain finger (40) that are provided in the active region and arranged alternately to allow each gate finger to be sandwiched between the source and drain fingers. The semiconductor device includes terminal circuit (60) that has inductive impedance at the frequency of a signal input to an input terminal of the one or more gate fingers, and is directly or indirectly connected to the one or more gate fingers at an area being spaced away from a connecting position of the input terminal (21a) of the one or more gate fingers (20).
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公开(公告)号：US20150340999A1
公开(公告)日：2015-11-26
申请号：US14640407
申请日：2015-03-06
发明人： Ko KANAYA
IPC分类号： H03F1/32
CPC分类号： H03F1/3241 , H03F1/3276 , H03F3/19 , H03F2200/387 , H03F2201/3215
摘要： A linearizer includes: an input terminal; an output terminal; a connection point connected between the input terminal and the output terminal; a diode connected to the connection point; a voltage terminal; and a resistor connected between the voltage terminal and the connection point, wherein 0 V is applied to the voltage terminal.
摘要翻译： 线性化装置包括：输入端; 输出端子; 连接在输入端和输出端之间的连接点; 连接到连接点的二极管; 电压端子; 以及连接在电压端子和连接点之间的电阻器，其中0V被施加到电压端子。
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公开(公告)号：US20230253347A1
公开(公告)日：2023-08-10
申请号：US18003245
申请日：2020-10-01
发明人： Ko KANAYA
IPC分类号： H01L23/62 , H01L23/00 , H01L23/495 , H01L23/04 , H01L23/66
CPC分类号： H01L23/62 , H01L24/85 , H01L23/49513 , H01L23/041 , H01L23/66 , H01L2924/1421 , H01L2223/6611 , H01L2223/6644
摘要： A semiconductor device (100) according to the present disclosure comprises a semiconductor chip (130) in which are formed a protruding terminal (14) that electrically connects to a transistor (13) and that has a greater cross-sectional area than a bonding wire (4) and a short circuit prevention side wall (15) that is insulating and that covers side surfaces that face the surroundings of the protruding terminal (14). The semiconductor chip (130) is bonded to the upper surface (3) of a metal plate (2) by a conductive bonding material 6. A conductor pattern (34a) that is formed in a circuit board (30) bonded to the upper surface (3) of the metal plate (2) is connected via the bonding wire (4) to the projection-direction end of the protruding terminal (14).
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公开(公告)号：US20200014339A1
公开(公告)日：2020-01-09
申请号：US16479009
申请日：2017-03-28
发明人： Ko KANAYA , Kazuya YAMAMOTO
IPC分类号： H03F1/32 , H01L29/20 , H01L29/872 , H01L29/861 , H03F3/195
摘要： A diode linearizer according to the present invention has parallelly mounting linearizer core units on a RF signal path via capacitors between the RF signal path and a ground, thus does not need a switch using an FET, for example, at a time of selectively operating a plurality of linearizer core units. Moreover, the diode linearizer does not need a capacitor in series for blocking a direct current between RF signal input and output terminals. Thus, a range of a gain which can be compensated by the diode linearizer can be increased. Furthermore, an insertion loss of the RF signal path in a state where the diode linearizer is off can be reduced, and a range of a gain expansion in operation can be increased. The switch is not used, or the number of elements of the capacitors which are needed is small, thus a circuit size is also small.
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公开(公告)号：US20160308499A1
公开(公告)日：2016-10-20
申请号：US14993131
申请日：2016-01-12
发明人： Naoki KOSAKA , Hiroaki MAEHARA , Ko KANAYA , Miyo MIYASHITA , Kazuya YAMAMOTO
CPC分类号： H01L23/66 , H01L25/072 , H01L2224/49175
摘要： In the present invention, in addition to arranging a plurality of amplifying elements in a staggered manner, signal path lengths from an input-side divider to gate pads of the plurality of amplifying elements are equalized, and signal path lengths from drain pads of the plurality of amplifying elements to an output-side combiner are equalized.
摘要翻译： 在本发明中，除了以交错方式布置多个放大元件之外，从多个放大元件的输入侧分频器到栅极焊盘的信号路径长度相等，并且来自多个放大元件的漏极焊盘的信号路径长度相等 放大元件到输出侧组合器是均衡的。
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