公开(公告)号：US20120295434A1

公开(公告)日：2012-11-22

申请号：US13473728

申请日：2012-05-17

Applicant: Moon-gi CHO ,  Sang-hee LEE ,  Jeong-woo PARK

Inventor： Moon-gi CHO ,  Sang-hee LEE ,  Jeong-woo PARK

IPC: H01L21/768

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/03 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/11902 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2924/01029 ,  H01L2924/01046

Abstract: A method of forming bumps of a semiconductor device with reduced solder bump collapse. The method includes preparing a semiconductor substrate in which pads are exposed externally from a passivation layer; forming a seed layer on the semiconductor substrate; forming a photoresist pattern to expose the seed layer on the pads; forming pillars by performing a primary electroplating on a region exposed by the photoresist pattern; forming a solder layer by performing a secondary electroplating on the pillars; removing the photoresist pattern; forming solder bumps, in which solders partially cover surfaces of the pillars, by performing a reflow process on the semiconductor substrate; and removing portions of the seed layer formed in regions other than the solder bumps.

Abstract translation: 一种形成具有减少的焊料凹陷的半导体器件的凸块的方法。 该方法包括制备其中焊盘从钝化层向外暴露的半导体衬底; 在半导体衬底上形成晶种层; 形成光致抗蚀剂图案以暴露焊盘上的种子层; 通过在由光致抗蚀剂图案曝光的区域上执行初级电镀形成柱; 通过在柱上进行二次电镀形成焊料层; 去除光致抗蚀剂图案; 通过对半导体衬底进行回流处理，形成焊料凸点，其中焊料部分地覆盖柱的表面; 以及除去形成在除了焊锡凸块之外的区域中的种子层的部分。

公开(公告)号：US20150364387A1

公开(公告)日：2015-12-17

申请号：US14729034

申请日：2015-06-02

Applicant: Moon-gi CHO ,  Eun-chul AHN ,  Jung-ho CHOI

Inventor： Moon-gi CHO ,  Eun-chul AHN ,  Jung-ho CHOI

IPC: H01L21/66 ,  H01L21/306 ,  H01L21/02 ,  H01L21/304

CPC classification number: H01L22/20 ,  B24B37/005 ,  B24B37/042 ,  B24B49/12 ,  H01L21/02016 ,  H01L21/02024 ,  H01L22/12

Abstract: A wafer polishing method includes first polishing for polishing a wafer backside of a wafer, detecting if a defect exists on the wafer backside, determining whether a level of the detected defect is not within an allowable range, if a defect exists on the wafer backside, and second polishing for repolishing the wafer backside if the level of the defect is within an allowable range. Accordingly, a wafer may be reprocessed so that a level of defects, which may be caused by performing grinding and polishing on the wafer backside, is within an allowable range. Thus, the wafer backside may have uniform quality, and a failure rate of the wafer during a manufacturing processed may be efficiently decreased.

Abstract translation: 晶片抛光方法包括：第一抛光用于抛光晶片的晶片背面，检测晶片背面是否存在缺陷;如果在晶片背面存在缺陷，则确定检测到的缺陷的水平是否不在容许范围内; 以及如果缺陷水平在允许范围内，则再次抛光晶片背面的第二抛光。 因此，可以对晶片进行再处理，使得可以通过在晶片背面进行研磨和研磨而引起的缺陷水平在允许范围内。 因此，晶片背面可以具有均匀的质量，并且可以有效地降低在制造加工期间晶片的故障率。

公开(公告)号：US20130082090A1

公开(公告)日：2013-04-04

申请号：US13614608

申请日：2012-09-13

Applicant: Moon-gi CHO ,  Hwan-sik LIM ,  Sun-hee PARK

Inventor： Moon-gi CHO ,  Hwan-sik LIM ,  Sun-hee PARK

IPC: B23K31/02 ,  B23K1/20

CPC classification number: H01L24/11 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14104 ,  H01L2224/14515 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01046 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2924/014

Abstract: Methods of forming connection bumps for semiconductor devices in which rewiring patterns are formed. The method includes preparing a semiconductor substrate on which a pad is partially exposed through a passivation film, forming a seed layer on the pad and passivation film, forming a photoresist pattern including an opening pattern comprising a first opening that exposes a portion of the seed layer on the pad and a second opening that exposes a portion of the seed layer on the passivation film and is separated from the first opening, performing a first electroplating to form filler layers in the opening patterns, performing a second electroplating to form a solder layer on the filler layers, removing the photoresist pattern and performing a reflow process to form a collapsed solder layer that electrically connects the filler layers to each other and a solder bump on the filler layer formed in the second opening.

Abstract translation: 形成重新布线图形的半导体器件的连接凸块的形成方法。 该方法包括制备其上通过钝化膜部分地暴露焊盘的半导体衬底，在焊盘和钝化膜上形成种子层，形成包括开口图案的光致抗蚀剂图案，该开口图案包括暴露种子层的一部分的第一开口 在所述焊盘上和第二开口，其暴露所述钝化膜上的所述种子层的一部分并且与所述第一开口分离，执行第一电镀以在所述开口图案中形成填充层，执行第二电镀以形成焊料层 填充层，去除光致抗蚀剂图案并进行回流处理，以形成将填充层彼此电连接的凹陷焊料层和形成在第二开口中的填料层上的焊料凸块。