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1.发明授权公开(公告)号：US09279064B2
公开(公告)日：2016-03-08
申请号：US13855629
申请日：2013-04-02
Applicant: NITTO DENKO CORPORATION
Inventor： Takashi Oda , Naohide Takamoto , Takeshi Matsumura
IPC: H01L21/00 , C09D171/08 , H01L23/00 , H01L21/78 , H01L23/31
CPC classification number: C09D171/08 , H01L21/78 , H01L23/3114 , H01L23/3164 , H01L23/562 , H01L2924/0002 , Y10T428/265 , Y10T428/31511 , H01L2924/00
Abstract: The present invention aims to provide a film for forming a protective layer that is capable of preventing cracks in a low dielectric material layer of a semiconductor wafer while suppressing an increase in the number of steps in the manufacture of a semiconductor device. This object is achieved by a film for forming a protective layer on a bumped wafer in which a low dielectric material layer is formed, including a support base, an adhesive layer, and a thermosetting resin layer, laminated in this order, wherein the melt viscosity of the thermosetting resin layer is 1×102 Pa·S or more and 2×104 Pa·S or less, and the shear modulus of the adhesive layer is 1×103 Pa or more and 2×106 Pa or less, when the thermosetting resin layer has a temperature in a range of 50 to 120° C.
Abstract translation: 本发明的目的在于提供一种形成保护层的膜，其能够防止半导体晶片的低电介质材料层中的裂纹，同时抑制半导体器件的制造中的步骤数量的增加。 该目的通过在其上形成低介电材料层的凸起晶片上形成保护层的膜来实现，该薄膜包括依次层叠的支撑基底，粘合层和热固性树脂层，其中熔体粘度 的热固性树脂层的摩尔比为1×102Pa·S以上且2×104Pa·S以下，粘合剂层的剪切模量为1×10 3 Pa以上2×10 6 Pa以下时， 树脂层的温度为50〜120℃。
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公开(公告)号：US08906746B2
公开(公告)日：2014-12-09
申请号：US13931525
申请日：2013-06-28
Applicant: Nitto Denko Corporation
Inventor： Takashi Oda , Kosuke Morita , Eiji Toyoda
IPC: H01L21/00 , H01L21/50 , H01L21/683 , H01L23/544 , H01L23/00 , H01L21/56 , H01L23/31
CPC classification number: H01L21/50 , H01L21/561 , H01L21/568 , H01L21/6836 , H01L23/3128 , H01L23/544 , H01L24/19 , H01L24/20 , H01L24/97 , H01L2221/68336 , H01L2223/54433 , H01L2223/54486 , H01L2224/02379 , H01L2224/04105 , H01L2924/01012 , H01L2924/01029 , H01L2924/12042 , H01L2924/15311 , H01L2924/00
Abstract: A method for producing a semiconductor device, including a semiconductor chip, for improving production efficiency and the flexibility of production design is provided. The method comprises: preparing a semiconductor chip having a first main surface on which an electroconductive member is formed; preparing a supporting structure in which, over a support configured to transmit radiation, a radiation curable pressure-sensitive adhesive layer and a first thermosetting resin layer are laminated in this order; arranging the semiconductor chips on the first thermosetting resin layer to face the first thermosetting resin layer to a second main surface of the semiconductor chips opposite to the first main surface; laminating a second thermosetting resin layer over the first thermosetting resin layer to cover the semiconductor chips; and curing the radiation curable pressure-sensitive adhesive layer by irradiating from the support side to peel the radiation curable pressure-sensitive adhesive layer from the first thermosetting resin layer.
Abstract translation: 提供一种用于制造半导体器件的方法，该半导体器件包括半导体芯片，用于提高生产效率和生产设计的灵活性。 该方法包括：制备具有形成有导电构件的第一主表面的半导体芯片; 制备其中在被配置为透射辐射的支撑件上，可辐射固化压敏粘合剂层和第一热固性树脂层按顺序层压的支撑结构; 将第一热固性树脂层上的半导体芯片布置成与第一主表面相对的半导体芯片的第二主表面面对第一热固性树脂层; 在第一热固性树脂层上层叠第二热固性树脂层以覆盖半导体芯片; 并且通过从支撑侧照射从第一热固性树脂层剥离可辐射固化压敏粘合剂层来固化可辐射固化压敏粘合剂层。
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3.发明公开公开(公告)号：US20230280554A1
公开(公告)日：2023-09-07
申请号：US18010561
申请日：2021-07-02
Applicant: NITTO DENKO CORPORATION
Inventor： Tadao Okawa , Takashi Oda , Masataka Yamaji , Kazushi Ichikawa
CPC classification number: G02B6/428 , H05K1/0274 , G02B6/4293
Abstract: An opto-electric hybrid board for an optical communication module in which an electric circuit part E including a pad for mounting an optical element, a pad for an optical element driving device, and an electrical interconnect line Y including an interconnect line portion A connecting the pads is provided on a first surface side of an insulative layer, and in which an optical waveguide W is on a second surface side of the insulative layer. A portion of a coverlay covering the electric circuit part E which overlaps the interconnect line portion A is removed to form an opening. The interconnect line portion A exposed through the opening is used as a terminal for a burn-in test of an optical element.
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公开(公告)号：US20230254973A1
公开(公告)日：2023-08-10
申请号：US18009063
申请日：2021-06-21
Applicant: NITTO DENKO CORPORATION
Inventor： Tadao Okawa , Takashi Oda , Masataka Yamaji , Kazushi Ichikawa
CPC classification number: H05K1/117 , H05K1/0271 , H05K1/144 , G02B6/12 , H05K2201/1034 , H05K2201/041 , H05K2201/10121
Abstract: An optical communication module substrate includes a wiring board and an opto-electronic hybrid substrate, the wiring board and the opto-electronic hybrid substrate being connected to each other, in which a connection terminal of the wiring board and a connection terminal of the opto-electronic hybrid substrate are electrical connection points, and a frame-shaped removal portion is formed by removing a portion of the metal reinforcing layer of the opto-electronic hybrid substrate that faces the connection terminal with the insulating layer interposed between the metal reinforcing layer and the connection terminal, so as to surround each terminal. According to this configuration, the connection strength at the connection point between the wiring board and the opto-electronic hybrid substrate is sufficiently ensured, and the optical communication module substrate has excellent electrical properties that are compatible with high-speed signal transmission.
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公开(公告)号：US11171514B2
公开(公告)日：2021-11-09
申请号：US16492484
申请日：2018-03-28
Applicant: NITTO DENKO CORPORATION
Inventor： Taiki Sueyoshi , Masami Inoue , Hisashi Tsuda , Takashi Oda , Kaoru Ito , Hideshi Yamakawa , Daigo Tsubai , Toru Mizutani , Yasuyuki Ota
Abstract: A wireless power transmission system includes a power-supplying device including an electronic oscillator that generates electric power having a frequency of 1 MHz or more and 5 MHz or less, and a power-supplying coil member in which the electric power flows; and a power-receiving device including a power-receiving coil member that is capable of generating electric power based on the magnetic field generating from the power-supplying coil member, wherein the power-receiving coil member is a sheet coil including an insulating layer and a first coil pattern disposed at one side of the insulating layer, the first coil pattern is composed of wires, and the wires are disposed in spaced apart relation from each other with a predetermined space provided therebetween in the radial direction of the first coil pattern.
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Patent Agency Ranking
公开(公告)号：US20140249269A1
公开(公告)日：2014-09-04
申请号：US14348947
申请日：2012-09-21
Applicant: NITTO DENKO CORPORATION
Inventor： Daisuke Uenda , Yusuke Shirakawa , Hiroshi Hamamoto , Takashi Oda , Eiji Toyoda , Takeshi Matsumura
IPC: C09D177/06
CPC classification number: C08G73/1082 , C08G73/1042 , C08G73/105 , C09D5/20 , C09D179/08
Abstract: In order to provide a thermally-detachable sheet that detaches at higher temperatures, this thermally-detachable sheet has a shear bond strength with respect to a silicon wafer of 0.25 kg/5×5 mm or larger, at a temperature of 200° C., after said temperature has been maintained for one minute, and a shear bond strength with respect to a silicon wafer of 0.25 kg/less than 5×5 mm at any temperature in a range of over 200° C. to not more than 500° C., after said temperature has been maintained for three minutes.
Abstract translation: 为了提供在较高温度下分离的可热拆卸的片材，该热分解片材在200℃的温度下具有相对于硅晶片的剪切粘合强度为0.25kg / 5×5mm或更大。 在超过200℃至不超过500℃的任何温度下，在所述温度保持1分钟之后，相对于硅晶片的剪切粘合强度为0.25kg /小于5×5mm 在所述温度保持3分钟之后。
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公开(公告)号：US08580619B2
公开(公告)日：2013-11-12
申请号：US13631286
申请日：2012-09-28
Applicant: Nitto Denko Corporation
Inventor： Takashi Oda , Kosuke Morita , Eiji Toyoda
IPC: H01L21/00
CPC classification number: H01L21/50 , H01L21/561 , H01L21/568 , H01L21/6836 , H01L23/3128 , H01L23/544 , H01L24/19 , H01L24/20 , H01L24/97 , H01L2221/68336 , H01L2223/54433 , H01L2223/54486 , H01L2224/02379 , H01L2224/04105 , H01L2924/01012 , H01L2924/01029 , H01L2924/12042 , H01L2924/15311 , H01L2924/00
Abstract: A method for producing a semiconductor device, including a semiconductor chip, for improving production efficiency and the flexibility of production design is provided. The method comprises: preparing a semiconductor chip having a first main surface on which an electroconductive member is formed; preparing a supporting structure in which, over a support configured to transmit radiation, a radiation curable pressure-sensitive adhesive layer and a first thermosetting resin layer are laminated in this order; arranging the semiconductor chips on the first thermosetting resin layer to face the first thermosetting resin layer to a second main surface of the semiconductor chips opposite to the first main surface; laminating a second thermosetting resin layer over the first thermosetting resin layer to cover the semiconductor chips; and curing the radiation curable pressure-sensitive adhesive layer by irradiating from the support side to peel the radiation curable pressure-sensitive adhesive layer from the first thermosetting resin layer.
Abstract translation: 提供一种用于制造半导体器件的方法，该半导体器件包括半导体芯片，用于提高生产效率和生产设计的灵活性。 该方法包括：制备具有形成有导电构件的第一主表面的半导体芯片; 制备其中在被配置为透射辐射的支撑件上，可辐射固化压敏粘合剂层和第一热固性树脂层按顺序层压的支撑结构; 将第一热固性树脂层上的半导体芯片布置成与第一主表面相对的半导体芯片的第二主表面面对第一热固性树脂层; 在第一热固性树脂层上层叠第二热固性树脂层以覆盖半导体芯片; 并且通过从支撑侧照射从第一热固性树脂层剥离可辐射固化压敏粘合剂层来固化可辐射固化压敏粘合剂层。
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公开(公告)号：US20130157419A1
公开(公告)日：2013-06-20
申请号：US13718821
申请日：2012-12-18
Applicant: NITTO DENKO CORPORATION
Inventor： Yusaku Shimizu , Shinya Akizuki , Takashi Oda , Eiji Toyoda , Takeshi Matsumura
IPC: H01L21/56
CPC classification number: H01L21/56 , H01L21/561 , H01L21/568 , H01L23/3107 , H01L24/96 , H01L2224/04105 , H01L2224/73267 , H01L2924/12042 , H01L2924/00
Abstract: The objective of the present invention is to provide a method of manufacturing a semiconductor device having less contamination of a semiconductor chip and good productivity. The present invention is a method of manufacturing a semiconductor device having a semiconductor chip, with the steps of preparing a plurality of semiconductor chips, preparing a resin sheet having a thermosetting resin layer, arranging the plurality of semiconductor chips on the thermosetting resin layer, arranging a cover film on the plurality of semiconductor chips, and embedding the plurality of semiconductor chips in the thermosetting resin layer by a pressure applied through the arranged cover film, in which the contact angle of the cover film to water is 90° or less.
Abstract translation: 本发明的目的是提供一种制造半导体芯片污染少且生产率高的半导体器件的方法。 本发明是一种制造具有半导体芯片的半导体器件的方法，其具有制备多个半导体芯片的步骤，制备具有热固性树脂层的树脂片，将多个半导体芯片布置在热固性树脂层上，布置 所述多个半导体芯片上的覆盖膜，并且通过所述布置的覆盖膜施加的压力将所述多个半导体芯片嵌入所述热固性树脂层中，所述覆盖膜与水的接触角为90°以下。
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公开(公告)号：US20130217187A1
公开(公告)日：2013-08-22
申请号：US13855629
申请日：2013-04-02
Applicant: Nitto Denko Corporation
Inventor： Takashi Oda , Naohide Takamoto , Takeshi Matsumura
IPC: C09D171/08 , H01L21/78
CPC classification number: C09D171/08 , H01L21/78 , H01L23/3114 , H01L23/3164 , H01L23/562 , H01L2924/0002 , Y10T428/265 , Y10T428/31511 , H01L2924/00
Abstract: The present invention aims to provide a film for forming a protective layer that is capable of preventing cracks in a low dielectric material layer of a semiconductor wafer while suppressing an increase in the number of steps in the manufacture of a semiconductor device. This object is achieved by a film for forming a protective layer on a bumped wafer in which a low dielectric material layer is formed, including a support base, an adhesive layer, and a thermosetting resin layer, laminated in this order, wherein the melt viscosity of the thermosetting resin layer is 1×102 Pa·S or more and 2×104 Pa·S or less, and the shear modulus of the adhesive layer is 1×103 Pa or more and 2×106 Pa or less, when the thermosetting resin layer has a temperature in a range of 50 to 120° C.
Abstract translation: 本发明的目的在于提供一种形成保护层的膜，其能够防止半导体晶片的低电介质材料层中的裂纹，同时抑制半导体器件的制造中的步骤数量的增加。 该目的通过在其上形成低介电材料层的凸起晶片上形成保护层的膜来实现，该薄膜包括依次层叠的支撑基底，粘合层和热固性树脂层，其中熔体粘度 的热固性树脂层的摩尔比为1×102Pa·S以上且2×104Pa·S以下，粘合剂层的剪切模量为1×10 3 Pa以上2×10 6 Pa以下时， 树脂层的温度为50〜120℃。
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公开(公告)号：US20230258893A1
公开(公告)日：2023-08-17
申请号：US18010564
申请日：2021-07-14
Applicant: NITTO DENKO CORPORATION
Inventor： Tadao Okawa , Takashi Oda , Masataka Yamaji , Kazushi Ichikawa
IPC: G02B6/42
CPC classification number: G02B6/428
Abstract: In an opto-electric hybrid board, an electric circuit part E is provided on a first surface side of an insulative layer, and includes pads for mounting an optical element, pads for a driving device for the optical element, and electrical interconnect lines Y including interconnect line portions A connecting the pads. A metal reinforcement layer and an optical waveguide W partially overlapping the metal reinforcement layer are provided on a second surface side of the insulative layer. A portion of the metal reinforcement layer which faces the interconnect line portions A on the opposite side of the insulative layer therefrom is removed to form an opening. This opto-electric hybrid board is capable of transmitting higher-frequency electric signals because the influence of the metal reinforcement layer on electrical properties is suppressed.
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