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38 条记录 (耗时 0.023 秒)

    DISCRETE-TIME CIRCUIT
    1.
    发明申请
    DISCRETE-TIME CIRCUIT 失效
    分离电路

    公开(公告)号：US20100207795A1

    公开(公告)日：2010-08-19

    申请号：US12612821

    申请日：2009-11-05

    申请人： Naoya Waki ,  Hirotomo Ishii

    发明人： Naoya Waki ,  Hirotomo Ishii

    IPC分类号： H03M3/00 ,  G06G7/12

    CPC分类号： H03M1/0658 ,  H03M1/0695 ,  H03M1/1245 ,  H03M1/44 ,  H03M3/326 ,  H03M3/35 ,  H03M3/43 ,  H03M3/454

    摘要： To reduce a random noise power included in an analog input signal, a discrete-time circuit samples an inputted analog signal a plurality of number of times at different times respectively and performs averaging processing on sampling results, thus enabling to respond appropriately even if an input signal has a high frequency without increasing a size of the circuit.

    摘要翻译： 为了减少包含在模拟输入信号中的随机噪声功率，离散时间电路分别在不同时间对输入的模拟信号多次采样，并对采样结果进行平均处理，因此即使输入 信号具有高频率而不增加电路的尺寸。

    Discrete-time circuit
    2.
    发明授权
    Discrete-time circuit 失效
    离散时间电路

    公开(公告)号：US08004435B2

    公开(公告)日：2011-08-23

    申请号：US12612821

    申请日：2009-11-05

    申请人： Naoya Waki ,  Hirotomo Ishii

    发明人： Naoya Waki ,  Hirotomo Ishii

    IPC分类号： H03M1/00

    CPC分类号： H03M1/0658 ,  H03M1/0695 ,  H03M1/1245 ,  H03M1/44 ,  H03M3/326 ,  H03M3/35 ,  H03M3/43 ,  H03M3/454

    摘要： To reduce a random noise power included in an analog input signal, a discrete-time circuit samples an inputted analog signal a plurality of number of times at different times respectively and performs averaging processing on sampling results, thus enabling to respond appropriately even if an input signal has a high frequency without increasing a size of the circuit.

    摘要翻译： 为了减少包含在模拟输入信号中的随机噪声功率，离散时间电路分别在不同时间对输入的模拟信号多次采样，并对采样结果进行平均处理，因此即使输入 信号具有高频率而不增加电路的尺寸。

    ANALOG-DIGITAL CONVERTER AND RECEIVER
    3.
    发明申请
    ANALOG-DIGITAL CONVERTER AND RECEIVER 有权
    模拟数字转换器和接收器

    公开(公告)号：US20130182803A1

    公开(公告)日：2013-07-18

    申请号：US13610499

    申请日：2012-09-11

    申请人： Hirotomo Ishii ,  Tomohiko Sugimoto ,  Masanori Furuta

    发明人： Hirotomo Ishii ,  Tomohiko Sugimoto ,  Masanori Furuta

    IPC分类号： H03M1/12 ,  H04B1/06

    CPC分类号： H03M1/687 ,  H03M1/468 ,  H03M1/765 ,  H03M1/804

    摘要： According to an embodiment, there are provided a capacitor DAC for generating an output signal in accordance with a connection state of a capacitor element, a reference voltage generation circuit for supplying a reference voltage to the capacitor DAC, a comparator for outputting a comparison result in accordance with the output signal, a successive approximation register for outputting a digital signal in accordance with the comparison result, and a control circuit for controlling a connection state of the capacitor element in accordance with the comparison result and comparing an ideal code with a digital signal obtained by sampling a predetermined voltage, thereby correcting an error of the digital signal.

    摘要翻译： 根据实施例，提供了一种用于根据电容器元件的连接状态产生输出信号的电容器DAC，用于向电容器DAC提供参考电压的参考电压产生电路，用于输出比较结果的比较器 根据输出信号，根据比较结果输出数字信号的逐次逼近寄存器和用于根据比较结果控制电容器元件的连接状态并将理想代码与数字信号进行比较的控制电路 通过对预定电压进行采样获得，从而校正数字信号的误差。

    A/D converter
    4.
    发明授权
    A/D converter 有权
    A / D转换器

    公开(公告)号：US07830295B2

    公开(公告)日：2010-11-09

    申请号：US12427495

    申请日：2009-04-21

    申请人： Shinichi Ikeda ,  Hirotomo Ishii ,  Yoshikazu Nagashima

    发明人： Shinichi Ikeda ,  Hirotomo Ishii ,  Yoshikazu Nagashima

    IPC分类号： H03M1/12

    CPC分类号： H03K5/2472 ,  H03M1/0678 ,  H03M1/468

    摘要： In an A/D converter, three capacitors are connected to a comparator. The A/D converter also includes three switching circuits that each input a first reference voltage, a second reference voltage, and a third reference voltage in the three capacitors. A control circuit selects at least two of the three switching circuits during a charging period of stray capacitance of each of the capacitors. The control circuit turns on one of the switching devices in the selected switching circuits simultaneously, and during a comparing period by the comparator, selects one of the three capacitors for each comparison, and selects another capacitor in the next comparison.

    摘要翻译： 在A / D转换器中，三个电容连接到比较器。 A / D转换器还包括三个开关电路，每个开关电路在三个电容器中输入第一参考电压，第二参考电压和第三参考电压。 在每个电容器的寄生电容的充电期间，控制电路选择三个开关电路中的至少两个。 控制电路同时接通选择的开关电路中的一个开关器件，并且在比较器的比较期间，为每个比较选择三个电容器中的一个，并在下一个比较中选择另一个电容器。

    Semiconductor integrated circuit apparatus
    6.
    发明申请
    Semiconductor integrated circuit apparatus 失效
    半导体集成电路装置

    公开(公告)号：US20050135033A1

    公开(公告)日：2005-06-23

    申请号：US11020069

    申请日：2004-12-20

    申请人： Nobutaka Kitagawa ,  Hirotomo Ishii

    发明人： Nobutaka Kitagawa ,  Hirotomo Ishii

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L23/60 ,  H01L23/62 ,  H01L27/02 ,  H02H3/20 ,  H02H9/00 ,  H03K17/00 ,  H03K19/0175

    CPC分类号： H01L27/0266 ,  H01L27/0292 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor integrated circuit device is disclosed, which comprises power supply system circuits, in which power supply terminals and/or ground terminals are separated from each other between the power supply system circuits, an electrostatic discharge protecting circuit, an internal circuit provided in each of the power supply system circuits, an internal signal transmitting line, a surge input detecting circuit, and at least one of an input protecting circuit which is provided at an input side of the internal circuit and which limits a voltage of a signal transmitted from the internal signal transmitting line, and an output logic setting circuit which is provided at an output side of the internal circuit and which sets a logic level of a signal outputted to the internal signal transmitting line to a low level when the surge input detecting circuit has detected a surge input.

    摘要翻译： 公开了一种半导体集成电路装置，其包括供电系统电路，其中电源端子和/或接地端子在电源系统电路之间彼此分离，静电放电保护电路，设置在每个 电源系统电路，内部信号传输线，浪涌输入检测电路，以及设置在内部电路的输入侧的输入保护电路中的至少一个，并限制从内部电路发送的信号的电压 信号发送线路和输出逻辑设置电路，其设置在内部电路的输出侧，并且当浪涌输入检测电路检测到一个信号时，将输出到内部信号发送线路的信号的逻辑电平设置为低电平 浪涌输入

    Residual signal generating circuit, successive approximation ad converter, pipelined ad converter, and radio receiver
    8.
    发明授权
    Residual signal generating circuit, successive approximation ad converter, pipelined ad converter, and radio receiver 失效
    剩余信号发生电路，逐次逼近广告转换器，流水线广告转换器和无线电接收器

    公开(公告)号：US08660506B2

    公开(公告)日：2014-02-25

    申请号：US13607365

    申请日：2012-09-07

    申请人： Masanori Furuta ,  Hirotomo Ishii

    发明人： Masanori Furuta ,  Hirotomo Ishii

    IPC分类号： G06F3/033 ,  H04K3/00

    CPC分类号： H03M1/168 ,  H03M1/162 ,  H03M1/361 ,  H03M1/804

    摘要： There is provided with a residual signal generating circuit in which the capacitive DA converter generates a first difference signal with respect to an input signal based on a criterion voltage, the criterion voltage being indicative of an input range of the input signal, the reference voltage generating circuit divides the criterion voltage to obtain at least one partial voltage signal, the residual signal generating section generates 2N−1 first residual signal according to a difference between the first difference signal and 2N−1−1 first reference signal, the 2N−1−1 first reference signal being 2N−1−1 partial voltage signal among said at least one partial voltage signal generated by the reference voltage generating circuit, the comparator compares the 2N−1 first residual signal with a fixed voltage to obtain 2N−1 first comparison signal each indicative of a logical value, and the decoder decodes the 2N−1 first comparison signal to obtain first data of N bits.

    摘要翻译： 设置有残留信号发生电路，其中电容DA转换器基于标准电压产生相对于输入信号的第一差分信号，标准电压指示输入信号的输入范围，产生参考电压 电路划分标准电压以获得至少一个部分电压信号，残差信号产生部分根据第一差信号和2N-1-1第一参考信号之间的差产生2N-1个第一残差信号， 1个第一参考信号是由参考电压产生电路产生的所述至少一个部分电压信号中的2N-1-1个部分电压信号，比较器将2N-1个第一残差信号与固定电压进行比较，以获得2N-1个第一比较 信号，每个指示逻辑值，并且解码器解码2N-1个第一比较信号以获得N位的第一数据。

    RESIDUAL SIGNAL GENERATING CIRCUIT, SUCCESSIVE APPROXIMATION AD CONVERTER, PIPELINED AD CONVERTER, AND RADIO RECEIVER
    9.
    发明申请
    RESIDUAL SIGNAL GENERATING CIRCUIT, SUCCESSIVE APPROXIMATION AD CONVERTER, PIPELINED AD CONVERTER, AND RADIO RECEIVER 失效
    残留信号发生电路，连续逼近AD转换器，管道AD转换器和无线电接收器

    公开(公告)号：US20130183920A1

    公开(公告)日：2013-07-18

    申请号：US13607365

    申请日：2012-09-07

    申请人： Masanori FURUTA ,  Hirotomo Ishii

    发明人： Masanori FURUTA ,  Hirotomo Ishii

    IPC分类号： H03M1/38 ,  H04B1/18 ,  H03M1/66

    CPC分类号： H03M1/168 ,  H03M1/162 ,  H03M1/361 ,  H03M1/804

    摘要： There is provided with a residual signal generating circuit in which the capacitive DA converter generates a first difference signal with respect to an input signal based on a criterion voltage, the criterion voltage being indicative of an input range of the input signal, the reference voltage generating circuit divides the criterion voltage to obtain at least one partial voltage signal, the residual signal generating section generates 2N−1 first residual signal according to a difference between the first difference signal and 2N−1−1 first reference signal, the 2N−1−1 first reference signal being 2N−1−1 partial voltage signal among said at least one partial voltage signal generated by the reference voltage generating circuit, the comparator compares the 2N−1 first residual signal with a fixed voltage to obtain 2N−1 first comparison signal each indicative of a logical value, and the decoder decodes the 2N−1 first comparison signal to obtain first data of N bits.

    摘要翻译： 设置有残留信号发生电路，其中电容DA转换器基于标准电压产生相对于输入信号的第一差分信号，标准电压指示输入信号的输入范围，产生参考电压 电路划分标准电压以获得至少一个部分电压信号，残差信号产生部分根据第一差信号和2N-1-1第一参考信号之间的差产生2N-1个第一残差信号， 1个第一参考信号是由参考电压产生电路产生的所述至少一个部分电压信号中的2N-1-1个部分电压信号，比较器将2N-1个第一残差信号与固定电压进行比较，以获得2N-1个第一比较 信号，每个指示逻辑值，并且解码器解码2N-1个第一比较信号以获得N位的第一数据。

    Network printing system, printing terminal and printing method
    10.
    发明授权
    Network printing system, printing terminal and printing method 有权
    网络打印系统，打印终端和打印方式

    公开(公告)号：US07675640B2

    公开(公告)日：2010-03-09

    申请号：US10810885

    申请日：2004-03-29

    申请人： Hirotomo Ishii ,  Norihisa Takayama

    发明人： Hirotomo Ishii ,  Norihisa Takayama

    IPC分类号： G06F15/00 ,  G06F9/44

    CPC分类号： H04L41/0883 ,  G06Q10/063 ,  H04L41/0853

    摘要： In a network printing system, initial print setting information and save-mode print setting information are preparatorily set as print setting information in a server. In response to a request from PC1 or PC2, the server sends the save-mode print setting information as the “print setting information” if the total number of print copies exceeds a predetermined number. If a user does not agree with the save-mode print setting information displayed on the PC1 or PC2, the user operates a button “no” in a confirmation dialogue and then resets the print setting information. A printing apparatus performs save-mode printing or normal printing in accordance with the set or reset print setting information. Therefore, an administrator of the network printing system has only to set the initial print setting information and the save-mode print setting information in the server. Thus, the network printing system allows print setting to be simply achieved.

    摘要翻译： 在网络打印系统中，初始打印设置信息和保存模式打印设置信息在服务器中被准备为打印设置信息。 响应于来自PC1或PC2的请求，如果打印副本总数超过预定数量，服务器将保存模式打印设置信息作为“打印设置信息”发送。 如果用户不同意PC1或PC2上显示的保存模式打印设置信息，则用户在确认对话中操作按钮“否”，然后重置打印设置信息。 打印装置根据所设置的或复位的打印设置信息执行保存模式打印或正常打印。 因此，网络打印系统的管理员仅在服务器中设置初始打印设置信息和保存模式打印设置信息。 因此，网络打印系统允许简单地实现打印设置。