公开(公告)号：US20050269634A1

公开(公告)日：2005-12-08

申请号：US10863830

申请日：2004-06-04

申请人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Matthew Copel ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Matthew Copel ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.

摘要翻译： 一种形成CMOS结构的方法及其制造的器件，具有改进的阈值电压和平带电压稳定性。 本发明的方法包括提供具有nFET区和pFET区的半导体衬底的步骤; 在所述半导体衬底上形成包括在高k电介质顶上的绝缘夹层的电介质叠层; 从nFET区域去除绝缘中间层而不从pFET区域去除绝缘中间层; 以及在pFET区域中提供至少一个栅极堆叠以及在nFET区域中提供至少一个栅极堆叠。 绝缘中间层可以是AlN或AlO x N y Y。 高k电介质可以是HfO 2，硅酸铪或铪硅氮氧化物。 可以通过包含HCl / H 2 O 2 O 2过氧化物溶液的湿蚀刻从nFET区域去除绝缘中间层。

公开(公告)号：US20050266663A1

公开(公告)日：2005-12-01

申请号：US11174738

申请日：2005-07-06

申请人： Nestor Bojarczuk ,  Matthew Copel ,  Supratik Guha ,  Vijay Narayanan

发明人： Nestor Bojarczuk ,  Matthew Copel ,  Supratik Guha ,  Vijay Narayanan

IPC分类号： H01L21/20 ,  H01L21/316 ,  H01L21/36

CPC分类号： H01L21/02488 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/31604 ,  H01L21/31691 ,  Y10S438/967

摘要： A method (and resultant structure) of forming a semiconductor structure, includes processing an oxide to have a crystalline arrangement, and depositing an amorphous semiconductor layer on the oxide by one of evaporation and chemical vapor deposition (CVD).

公开(公告)号：US20060275977A1

公开(公告)日：2006-12-07

申请号：US11500254

申请日：2006-08-07

申请人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Matthew Copel ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Matthew Copel ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L21/8238

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.

公开(公告)号：US20050269635A1

公开(公告)日：2005-12-08

申请号：US10957342

申请日：2004-10-01

申请人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Matthew Copel ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Matthew Copel ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： The present invention provides a semiconductor structure comprising a semiconductor substrate having source and drain diffusion regions located therein, the source and drain diffusion regions being separated by a device channel; and a gate stack located on top of the device channel, the gate stack comprising a high-k gate dielectric, an insulating interlayer and a fully silicided metal gate conductor, the insulating interlayer located between the high-k gate dielectric and the fully silicided metal gate conductor, wherein the insulating interlayer is capable of stabilizing threshold voltage and flatband voltage of the semiconductor structure to a targeted value.

摘要翻译： 本发明提供一种半导体结构，其包括具有位于其中的源极和漏极扩散区域的半导体衬底，源极和漏极扩散区域被器件沟道分离; 以及位于器件沟道顶部的栅极堆叠，栅极堆叠包括高k栅极电介质，绝缘中间层和完全硅化金属栅极导体，位于高k栅极电介质和完全硅化金属之间的绝缘中间层 栅极导体，其中所述绝缘中间层能够将所述半导体结构的阈值电压和平带电压稳定到目标值。

公开(公告)号：US20060244035A1

公开(公告)日：2006-11-02

申请号：US11118521

申请日：2005-04-29

申请人： Nestor Bojarczuk ,  Michael Chudzik ,  Matthew Copel ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Nestor Bojarczuk ,  Michael Chudzik ,  Matthew Copel ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L29/76

CPC分类号： H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/517

摘要： The present invention provides a metal stack structure that stabilizes the flatband voltage and threshold voltages of material stacks that include a Si-containing conductor and a Hf-based dielectric. This present invention stabilizes the flatband voltages and the threshold voltages by introducing a rare earth metal-containing layer into the material stack that introduces, via electronegativity differences, a shift in the threshold voltage to the desired voltage. Specifically, the present invention provides a metal stack comprising a hafnium-based dielectric; a rare earth metal-containing layer located atop of, or within, said hafnium-based dielectric; an electrically conductive capping layer located above said hafnium-based dielectric; and a Si-containing conductor.

摘要翻译： 本发明提供一种金属堆叠结构，其稳定包括含Si导体和Hf基电介质的材料堆叠的平带电压和阈值电压。 本发明通过将含稀土金属的层引入材料堆中来稳定平带电压和阈值电压，其通过电负性差异将阈值电压的偏移引入期望的电压。 具体地说，本发明提供一种包含铪基电介质的金属叠层; 位于所述铪基电介质的顶部或内部的含稀土金属的层; 位于所述铪基电介质上方的导电覆盖层; 和含Si导体。

公开(公告)号：US20050258491A1

公开(公告)日：2005-11-24

申请号：US10845719

申请日：2004-05-14

申请人： Nestor Bojarczuk ,  Eduard Cartier ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Vijay Narayanan

发明人： Nestor Bojarczuk ,  Eduard Cartier ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Vijay Narayanan

IPC分类号： H01L21/8234 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786 ,  H01L51/00 ,  H01L51/05

CPC分类号： H01L21/28202 ,  H01L21/28194 ,  H01L21/823857 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： An insulating interlayer for use in complementary metal oxide semiconductor (CMOS) that prevents unwanted shifts in threshold voltage and flatband voltage is provided. The insulating interlayer is located between a gate dielectric having a dielectric constant of greater than 4.0 and a Si-containing gate conductor. The insulating interlayer of the present invention is any metal nitride, that optionally may include oxygen, that is capable of stabilizing the threshold and flatband voltages. In a preferred embodiment, the insulating interlayer is aluminum nitride or aluminum oxynitride and the gate dielectric is hafnium oxide, hafnium silicate or hafnium silicon oxynitride. The present invention is particularly useful in stabilizing the threshold and flatband voltage of p-type field effect transistors.

摘要翻译： 提供了用于防止阈值电压和平带电压的不期望的偏移的互补金属氧化物半导体（CMOS）中的绝缘夹层。 绝缘中间层位于介电常数大于4.0的栅极电介质和含Si的栅极导体之间​​。 本发明的绝缘中间层是能够稳定阈值和平带电压的任何金属氮化物，其可任选地包括氧。 在优选实施例中，绝缘中间层为氮化铝或氮氧化铝，栅极电介质为氧化铪，硅酸铪或铪硅氮氧化物。 本发明在稳定p型场效应晶体管的阈值和平带电压方面特别有用。

公开(公告)号：US20060102968A1

公开(公告)日：2006-05-18

申请号：US10988733

申请日：2004-11-15

申请人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Paul Jamison ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Paul Jamison ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L29/94

CPC分类号： H01L29/513 ,  H01L21/28194 ,  H01L21/2822 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518

摘要： A semiconductor structure is provided that includes a Vt stabilization layer between a gate dielectric and a gate electrode. The Vt stabilization layer is capable of stabilizing the structure's threshold voltage and flatband voltage to a targeted value and comprises a nitrided metal oxide, or a nitrogen-free metal oxide, with the proviso that when the Vt stabilization layer comprises a nitrogen-free metal oxide, at least one of the semiconductor substrate or the gate dielectric includes nitrogen. The present invention also provides a method of fabricating such a structure.

摘要翻译： 提供了一种半导体结构，其包括在栅极电介质和栅电极之间的V 1稳定层。 VST稳定层能够将结构的阈值电压和平带电压稳定到目标值，并且包括氮化金属氧化物或无氮金属氧化物，条件是当V < 稳定层包括无氮金属氧化物，半导体衬底或栅极电介质中的至少一个包括氮。 本发明还提供一种制造这种结构的方法。

公开(公告)号：US20050095815A1

公开(公告)日：2005-05-05

申请号：US10998840

申请日：2004-11-30

申请人： Nestor Bojarczuk ,  Douglas Buchanan ,  Supratik Guha ,  Vijay Narayanan ,  Lars-Ake Ragnarsson

发明人： Nestor Bojarczuk ,  Douglas Buchanan ,  Supratik Guha ,  Vijay Narayanan ,  Lars-Ake Ragnarsson

IPC分类号： H01L21/316 ,  H01L21/30

CPC分类号： H01L21/02192 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/02293 ,  H01L21/31604

摘要： A method (and resultant structure) of forming a semiconductor structure, includes forming a mixed rare earth oxide on silicon. The mixed rare earth oxide is lattice-matched to silicon.

摘要翻译： 形成半导体结构的方法（和结果）包括在硅上形成混合的稀土氧化物。 混合的稀土氧化物与硅晶格匹配。

公开(公告)号：US20060246740A1

公开(公告)日：2006-11-02

申请号：US11119310

申请日：2005-04-29

申请人： Eduard Cartier ,  Matthew Copel ,  Supratik Guha ,  Richard Haight ,  Fenton McFeely ,  Vijay Narayanan

发明人： Eduard Cartier ,  Matthew Copel ,  Supratik Guha ,  Richard Haight ,  Fenton McFeely ,  Vijay Narayanan

IPC分类号： H01L21/31

CPC分类号： H01L21/823462 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/31691 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4958 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a method for removing charged defects from a material stack including a high k gate dielectric and a metal contact such that the final gate stack, which is useful in forming a pFET device, has a threshold voltage substantially within the silicon band gap and good carrier mobility. Specifically, the present invention provides a re-oxidation procedure that will restore the high k dielectric of a pFET device to its initial, low-defect state. It was unexpectedly determined that by exposing a material stack including a high k gate dielectric and a metal to dilute oxygen at low temperatures will substantially eliminate oxygen vacancies, resorting the device threshold to its proper value. Furthermore, it was determined that if dilute oxygen is used, it is possible to avoid undue oxidation of the underlying semiconductor substrate which would have a deleterious effect on the capacitance of the final metal-containing gate stack. The present invention also provides a semiconductor structure that includes at least one gate stack that has a threshold voltage within a control range and has good carrier mobility.

公开(公告)号：US08193051B2

公开(公告)日：2012-06-05

申请号：US13047172

申请日：2011-03-14

申请人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： H01L21/8238

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.

摘要翻译： 本发明提供一种半导体结构，其包括具有位于其中的多个源极和漏极扩散区域的半导体衬底，每对源极和漏极扩散区域由器件沟道分离。 该结构还包括位于一些器件通道顶部的pFET器件的第一栅极堆叠，第一栅极堆叠包括高k栅极电介质，邻接栅极电介质的绝缘夹层和邻接绝缘体的完全硅化金属栅电极 中间层，绝缘中间层包括将p-FET器件的阈值电压和扁平带电压稳定到目标值的绝缘金属氮化物，并且是氮氧化铝，氮化硼，氮氧化硼，氮化镓，氮氧化镓，氮化铟和铟中的一种 氮氧化物。 nFET器件的第二栅极堆叠位于顶部剩余器件沟道上，第二栅极堆叠包括高k栅极电介质和直接位于高k栅极电介质顶部的完全硅化栅电极。