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12 条记录 (耗时 0.018 秒)

    Thin film forming apparatus having adjustable guide
    3.
    发明授权
    Thin film forming apparatus having adjustable guide 失效
    薄膜成型设备具有可调节指导

    公开(公告)号：US5086727A

    公开(公告)日：1992-02-11

    申请号：US573240

    申请日：1990-08-24

    申请人： Mikio Sekiguchi ,  Mizuho Imai ,  Nobuyasu Shiba ,  Hideyo Iida

    发明人： Mikio Sekiguchi ,  Mizuho Imai ,  Nobuyasu Shiba ,  Hideyo Iida

    IPC分类号： C23C18/02 ,  B05B13/00 ,  C03C17/00 ,  C23C18/12 ,  H01B5/14 ,  H01B13/00 ,  H01L21/283 ,  H01L21/288 ,  H01L31/042

    CPC分类号： C03C17/002 ,  B05B13/00

    摘要： A thin film forming apparatus which forms a thin film over a surface of a subtrate by spraying a mist of a source solution produced by atomization over the surface of the substrate heated to a given temperature. The film forming apparatus is provided with a pair of guide members for supporting and guiding the substrate at opposite sides of the same. The distance between the opposite inner surfaces of the guide members can be changed according to the width of the substrate to be supported and guided by the pair of guide members. The distance between the respective lower portions of the opposite inner surfaces of the pair of guide members is greater than the distance between the upper portions of the opposite inner surfaces of the same, so that the distribution of the flow rate per unit flow passage area of the mist of the source solution is uniform with respect to the width of the substrate and enables a thin film of a uniform thickness to be formed over the entire surface of the substrate.

    Semiconductor memory device having transfer gates which prevent high voltages from being applied to memory and dummy cells in the reading operation
    6.
    发明授权
    Semiconductor memory device having transfer gates which prevent high voltages from being applied to memory and dummy cells in the reading operation 失效
    具有在读取操作中防止高电压施加到存储器和虚设单元的传输门的半导体存储器件

    公开(公告)号：US5138579A

    公开(公告)日：1992-08-11

    申请号：US632613

    申请日：1990-12-26

    申请人： Yuuichi Tatsumi ,  Hidenobu Minagawa ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Mizuho Imai

    发明人： Yuuichi Tatsumi ,  Hidenobu Minagawa ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Mizuho Imai

    IPC分类号： G11C7/00 ,  G11C16/06 ,  G11C16/28 ,  G11C17/00

    CPC分类号： G11C16/28

    摘要： A semiconductor memory device includes word lines selectively driven by a signal from a row decoder, memory cells connected to word lines, first and second data lines, a bit line connected to receive data from the memory cell and to supply received data to the first data lines, dummy cells connected to word lines, first and second dummy data lines, a dummy bit lines connected to receive data from the dummy memory cell and to supply received data to the first dummy data line, a data sensing circuit for generating an output signal corresponding to a potential difference between the second data line and second dummy data line, a first MOS transistor connected between the first and second data lines, a first load circuit for charging the second data line, a second MOS transistor connected between the first and second dummy data lines, and a second load circuit for charging the second dummy data lines. The memory device further includes a first equalizer circuit connected between the second data line and dummy data line and equalizing potentials at both ends during a predetermined period of time after the semiconductor memory device is set in the active mode, and a second equalizer circuit connected between the data line and dummy data line and equalizing potential as at both ends during a predetermined period of time after the memory device is set in the active mode.

    摘要翻译： 半导体存储器件包括由来自行解码器的信号选择性地驱动的字线，连接到字线的存储器单元，第一和第二数据线，连接到从存储器单元接收数据并将接收到的数据提供给第一数据的位线 连接到字线的虚拟单元，第一和第二虚拟数据线，连接成从虚拟存储单元接收数据并将接收到的数据提供给第一虚拟数据线的虚拟位线;数据感测电路，用于产生输出信号 对应于第二数据线和第二虚拟数据线之间的电位差，连接在第一和第二数据线之间的第一MOS晶体管，用于对第二数据线充电的第一负载电路，连接在第一和第二数据线之间的第二MOS晶体管 虚拟数据线，以及用于对第二虚拟数据线进行充电的第二负载电路。 存储装置还包括连接在第二数据线和虚拟数据线之间的第一均衡器电路，并且在半导体存储器件被设置为激活模式之后的预定时间段期间使两端的电位相等，以及第二均衡器电路 数据线和虚拟数据线，并且在存储器件被设置为活动模式之后的预定时间段期间两端的均衡电位。

    Semiconductor memory device with redundancy circuit
    9.
    发明授权
    Semiconductor memory device with redundancy circuit 失效
    具有冗余电路的半导体存储器件

    公开(公告)号：US4858192A

    公开(公告)日：1989-08-15

    申请号：US225510

    申请日：1988-07-28

    申请人： Yuuichi Tatsumi ,  Hidenobu Minagawa ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Mizuho Imai

    发明人： Yuuichi Tatsumi ,  Hidenobu Minagawa ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Mizuho Imai

    IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04

    CPC分类号： G11C29/781

    摘要： A semiconductor memory device has a redundancy circuit for compensating a defective bit when it occurs in the main memory cells. The redundancy circuit includes spare memory cells, a spare row decoder for selecting the spare memory cells, a first circuit section for inhibiting the use of the main row decoder when the spare row decoder is used, and a second circuit section for selecting the spare row decoder when an address specifying the main row line connected to the defective memory cell is denoted.

    摘要翻译： 半导体存储器件具有用于在发生在主存储器单元中时补偿有缺陷的位的冗余电路。 冗余电路包括备用存储单元，用于选择备用存储单元的备用排解码器​​，当使用备用行解码器时禁止使用主行解码器的第一电路部分和用于选择备用行的第二电路部分 解码器，当指定连接到有缺陷的存储单元的主行线的地址被表示时。