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公开(公告)号：US09287867B2
公开(公告)日：2016-03-15
申请号：US14295658
申请日：2014-06-04
申请人： Onkyo Corporation
CPC分类号： H03K19/0002 , H03K19/09443 , H03K19/21 , H03M3/30 , H04L25/4923 , H04L25/4925
摘要： A circuit having versatility synthesizes one-bit digital signals to generate a ternary signal. The pulse synthesizing circuit synthesizes one-bit digital signals from two DFFs to generate a ternary signal. The pulse synthesizing circuit has a first NOR gate, a second NOR gate, a third NOR gate, and three switches. The first switch is connected to a first electric potential, the second switch is connected to a second electric potential, and the third switch is connected to a third electric potential. The first to third switches are turned on/off according to logical values of the signals from the two DFFs, and any of the first electric potential, the second electric potential, and the third electric potential is set as an output potential so that a ternary signal is generated.
摘要翻译： 具有通用性的电路合成一位数字信号以产生三进制信号。 脉冲合成电路从两个DFF合成一位数字信号，生成三态信号。 脉冲合成电路具有第一或非门，第二或非门，第三或非门和三个开关。 第一开关连接到第一电位，第二开关连接到第二电位，第三开关连接到第三电位。 根据来自两个DFF的信号的逻辑值，第一至第三开关被接通/断开，并且将第一电位，第二电位和第三电位中的任一个设置为输出电位，使得三元 生成信号。
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公开(公告)号：US09762197B2
公开(公告)日：2017-09-12
申请号：US15238644
申请日：2016-08-16
申请人： Onkyo Corporation
发明人： Kei Asao , Tsuyoshi Kawaguchi , Makoto Yoshida , Takanori Shiozaki , Yoshinori Nakanishi , Hiroyuki Asahara , Norimasa Kitagawa
CPC分类号： H03G3/341 , H03F1/26 , H03F3/183 , H03F3/187 , H03F3/45475 , H03F3/72 , H03F2200/03 , H03G3/348 , H03M1/66 , H04R5/04
摘要： To realize active control ground that sets inverted output of an amplification circuit to ground with simple configuration.A DAP 1 comprises a positive side DAC 7 that D/A-converts digital audio data into analog audio data, a positive side amplification circuit 9 that amplifies the analog audio data that the DAC 7 D/A-converts, a negative side DAC 8 that D/A-converts the digital audio data into the analog audio data, and a negative side amplification circuit 10 that amplifies the analog audio data that the DAC 8 D/A-converts, and a CPU 2. The CPU 2 mutes the DAC 8 in case of an ACG mode that sets output of the amplification circuit 10 to ground.
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公开(公告)号：US09350378B2
公开(公告)日：2016-05-24
申请号：US14295587
申请日：2014-06-04
申请人： Onkyo Corporation
CPC分类号： H03M3/37 , G11B20/10009 , G11B2020/00065 , H03M3/30 , H03M3/346 , H03M3/348 , H03M3/424 , H04R3/00
摘要： Provided is a modulation circuit that can correct an output state in real time and reliably modulate an input signal to output the modulated signal. The signal modulation circuit includes a subtracter, an integrator, a chopper circuit, a frequency divider, and a D-type flip-flop. A delay circuit of a sigma delta modulation circuit is not provided to a feedback circuit, and a signal is delayed and quantized in the D-type flip-flop. The chopper circuit inserts a zero level at timing synchronized with a clock signal, so that pulse density modulation is performed.
摘要翻译： 提供了可以实时校正输出状态并可靠地调制输入信号以输出调制信号的调制电路。 信号调制电路包括减法器，积分器，斩波电路，分频器和D型触发器。 Σ-Δ调制电路的延迟电路不提供给反馈电路，并且在D型触发器中延迟和量化信号。 斩波电路在与时钟信号同步的定时插入零电平，从而执行脉冲密度调制。
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公开(公告)号：US09240783B2
公开(公告)日：2016-01-19
申请号：US14295658
申请日：2014-06-04
申请人： Onkyo Corporation
摘要： A circuit having versatility synthesizes one-bit digital signals to generate a ternary signal. The pulse synthesizing circuit synthesizes one-bit digital signals from two DFFs to generate a ternary signal. The pulse synthesizing circuit has a first NOR gate, a second NOR gate, a third NOR gate, and three switches. The first switch is connected to a first electric potential, the second switch is connected to a second electric potential, and the third switch is connected to a third electric potential. The first to third switches are turned on/off according to logical values of the signals from the two DFFs, and any of the first electric potential, the second electric potential, and the third electric potential is set as an output potential so that a ternary signal is generated.
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公开(公告)号：US09246457B2
公开(公告)日：2016-01-26
申请号：US13963549
申请日：2013-08-09
申请人： ONKYO CORPORATION
发明人： Tsuyoshi Kawaguchi
摘要： An amplifying device is provided that reduces power consumption and quickly starts amplification of an audio signal of a channel to be used. A control section 17 inputs a control signal for instructing operation or standby into post-amplifying sections 11b and 12b, and inputs a control signal for instructing standby to post-amplifying sections 13b and 14b. In the post-amplifying section 11b, when the control signal for instructing standby or operation is input from the control section 17, a modulation circuit 52 modulates the analog audio signal into a switching signal. An output stage circuit 54 amplifies the output signal. When the control signal for instructing the operation is input from the control section 17, a driving circuit 53 drives the output stage circuit 54 in response to the switching signal, and stops the driving of the output stage circuit 54 when the control signal for instructing standby is input.
摘要翻译： 提供一种放大装置，其降低功耗并且快速开始对要使用的信道的音频信号的放大。 控制部分17将用于指示操作或待机的控制信号输入到后置放大部分11b和12b中，并且将用于指示待机的控制信号输入到后置放大部分13b和14b。 在后置放大部分11b中，当从控制部分17输入用于指示待命或操作的控制信号时，调制电路52将模拟音频信号调制成切换信号。 输出级电路54放大输出信号。 当从控制部分17输入用于指示操作的控制信号时，驱动电路53响应于切换信号驱动输出级电路54，并且当用于指示待机的控制信号时停止输出级电路54的驱动 是输入。
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公开(公告)号：US10243516B2
公开(公告)日：2019-03-26
申请号：US15888031
申请日：2018-02-04
申请人： ONKYO CORPORATION
摘要： A first circuit unit of an audio amplifier includes a first emitter follower connected to an pre stage input terminal, a second emitter follower connected to an pre stage input terminal, a main transistor connected to an output path of the first emitter follower and an output path of the second emitter follower, a first resistor and a second resistor, which are series-connected between the output path of the first emitter follower and a DC voltage source, and a zener diode connected to a series-connection point between the first resistor and the second resistor. A second circuit unit has a circuit configuration that is complementary to the first circuit unit. A path leading to a collector of each transistor configuring the first and second emitter followers in one of the circuit units is connected to the series-connection point in the other circuit unit.
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公开(公告)号：US10149053B2
公开(公告)日：2018-12-04
申请号：US15657142
申请日：2017-07-22
申请人： Onkyo Corporation
发明人： Hiroki Kurosaki , Tsuyoshi Kawaguchi , Yoshinori Nakanishi , Hiroyuki Asahara , Norimasa Kitagawa
摘要： To resolve volume shortage of middle and high band of speaker reproduction sound. A DSP 4 performs LPF processing to extract low frequency component of an audio signal to which the first volume processing is performed, DRC processing to compress the audio signal to which the LPF processing is performed in case that the audio signal to which the LPF processing is performed is not less than a predetermined signal level, HPF processing to extract high frequency component of the audio signal to which the first volume processing is performed, second volume processing to attenuate the audio signal to which the HPF processing is performed based on the volume value that is received, and synthesis processing to synthesize the audio signal to which the DRC processing is performed and the audio signal to which the second volume processing is performed.
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公开(公告)号：US09787319B2
公开(公告)日：2017-10-10
申请号：US15137129
申请日：2016-04-25
申请人： Onkyo Corporation
CPC分类号： H03M3/37 , G11B20/10009 , G11B2020/00065 , H03M3/30 , H03M3/346 , H03M3/348 , H03M3/424 , H04R3/00
摘要： Provided is a modulation circuit that can correct an output state in real time and reliably modulate an input signal to output the modulated signal. The signal modulation circuit includes a subtractor, an integrator, a chopper circuit, a frequency divider, and a D-type flip-flop. A delay circuit of a sigma delta modulation circuit is not provided to a feedback circuit, and a signal is delayed and quantized in the D-type flip-flop. The chopper circuit inserts a zero level at timing synchronized with a clock signal, so that pulse density modulation is performed.
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公开(公告)号：US09712919B2
公开(公告)日：2017-07-18
申请号：US15238634
申请日：2016-08-16
申请人： Onkyo Corporation
发明人： Kei Asao , Tsuyoshi Kawaguchi , Makoto Yoshida , Takanori Shiozaki , Yoshinori Nakanishi , Hiroyuki Asahara , Norimasa Kitagawa
CPC分类号： H04R5/033 , H03F3/187 , H03F3/45475 , H03F3/72 , H03F2200/03 , H03F2203/7227 , H03M1/66 , H04R5/04
摘要： To reduce signal output and wiring to a D/A converter (DAC).A DAP 1 comprises a DAC 7 that D/A-converts LR 2 channels digital audio data into LR 2 channels analog audio data, an amplification circuit 9 that amplifies the LR 2 channels analog audio data that the DAC 7 D/A-converts, a DAC 8 that D/A-converts the LR 2 channels digital audio data into the LR 2 channels analog audio data, and an amplification circuit 10 that amplifies inverted LR 2 channels analog audio data that the LR 2 channels analog audio data that the DAC 8 D/A-converts is inverted.
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公开(公告)号：US09590654B2
公开(公告)日：2017-03-07
申请号：US14594329
申请日：2015-01-12
申请人： Onkyo Corporation
IPC分类号： H03M3/00
摘要： Provided is a circuit which can correct an output state in real time and reduce influences of distortion/noise components generated by a delay device. A signal modulation circuit includes a subtractor, an integrator, a phase inverting circuit, a DFF for while inserting a zero level at timing synchronous with the clock signal, delaying and quantizing the signal, a ternary signal generating circuit for generating a ternary signal for selectively driving a load connected to a single power supply into ternary conductive states including a positive current on-state, a negative current on-state, and an off-state, a driver circuit for generating a driving signal for driving a load, and a feedback circuit for feeding back the driving signal from the driver circuit to the input signal.
摘要翻译： 提供了可以实时校正输出状态并减少由延迟装置产生的失真/噪声分量的影响的电路。 信号调制电路包括减法器，积分器，相位反相电路，用于在与时钟信号同步的定时插入零电平的DFF，对信号进行延迟和量化;三态信号发生电路，用于选择性地产生三态信号 将连接到单个电源的负载驱动为包括正电流导通状态，负电流导通状态和截止状态的三态导通状态，用于产生用于驱动负载的驱动信号的驱动电路和反馈 用于将驱动信号从驱动电路反馈到输入信号的电路。
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