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公开(公告)号：US4377819A
公开(公告)日：1983-03-22
申请号：US032017
申请日：1979-04-20
申请人： Yoshio Sakai , Toshiaki Masuhara , Osamu Minato , Toshio Sasaki , Hisao Katto , Norikazu Hashimoto , Shin-ichi Muramatsu , Akihiro Tomozawa
发明人： Yoshio Sakai , Toshiaki Masuhara , Osamu Minato , Toshio Sasaki , Hisao Katto , Norikazu Hashimoto , Shin-ichi Muramatsu , Akihiro Tomozawa
IPC分类号： G11C11/412 , H01L21/02 , H01L21/318 , H01L21/822 , H01L27/04 , H01L27/06 , H01L27/11 , H01L29/06 , H01L29/40 , H01L29/41 , H01L29/04
CPC分类号： H01L29/402 , H01L21/3185 , H01L27/0605 , H01L27/1112 , H01L28/20 , H01L29/41
摘要： A semiconductor device including at least a resistance element formed of polycrystalline silicon having a high resistivity. An electrode is provided on the high resistance polycrystalline silicon region with a silicon dioxide film and a silicon nitride film being interposed therebetween. The electrode is coupled to the ground potential. In this manner, high stability is obtained in the behavior of the resistance element inasmuch as the formation of a parasitic MOS device under said high resistance region is suppressed, and the threshold voltage of any such MOS device is made raised.
摘要翻译： 一种半导体器件，至少包括由具有高电阻率的多晶硅形成的电阻元件。 在具有二氧化硅膜的高电阻多晶硅区域上设置电极，并且在其间插入有氮化硅膜。 电极与地电位耦合。 以这种方式，由于抑制了在所述高电阻区域下的寄生MOS器件的形成，所以电阻元件的性能得到了很高的稳定性，并且提高了任何这种MOS器件的阈值电压。
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公开(公告)号：US4015281A
公开(公告)日：1977-03-29
申请号：US121375
申请日：1971-03-05
IPC分类号： H01L21/765 , H01L27/088 , H01L29/51 , H01L27/02
CPC分类号： H01L29/511 , H01L21/765 , H01L27/0883
摘要： An enhancement-type and a depletion-type metal-insulator-semiconductor field effect transistor are formed on a common substrate of silicon and are electrically isolated from each other by a plurality of layers including, for example, a first layer of SiO.sub.2, a second layer of Al.sub.2 O.sub.3 capable of inducing holes in the surface portion of the substrate, and a third layer of SiO.sub.2, and the relation between the thicknesses of these layers is suitably selected for attaining the satisfactory isolation between these transistors.
摘要翻译： 增强型和耗尽型金属 - 绝缘体 - 半导体场效应晶体管形成在公共的硅衬底上，并且通过多个层彼此电隔离，所述多个层包括例如第一SiO 2层，第二层 能够在衬底的表面部分中引入空穴的Al 2 O 3层和SiO 3层，并且适当地选择这些层的厚度之间的关系以获得这些晶体管之间的令人满意的隔离。
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公开(公告)号：US4355374A
公开(公告)日：1982-10-19
申请号：US172378
申请日：1980-07-24
IPC分类号： G11C11/401 , G11C11/404 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/78 , G11C11/40 , G11C11/24
CPC分类号： G11C11/404 , H01L27/10805 , H01L27/10808
摘要： A semiconductor memory comprising a memory cell disposed on a p-type semiconductor substrate and including an insulated-gate field effect transistor and a storage capacitor. The storage capacitor comprises: an insulator capacitor including a first electrode disposed on the substrate, a film of Si.sub.3 N.sub.4 disposed on the first electrode, and a second electrode disposed on the Si.sub.3 N.sub.4 film; and a pn junction capacitor including a first n-type impurity region for constituting either the source or drain of the insulated-gate field effect transistor, and a second p-type impurity region disposed in contact with the first impurity region and having a higher impurity concentration than the substrate.
摘要翻译： 一种半导体存储器，包括设置在p型半导体衬底上并包括绝缘栅场效应晶体管和存储电容器的存储单元。 存储电容器包括：绝缘体电容器，包括设置在基板上的第一电极，设置在第一电极上的Si 3 N 4膜和设置在Si 3 N 4膜上的第二电极; 以及包含用于构成绝缘栅场效应晶体管的源极或漏极的第一n型杂质区和与第一杂质区接触并具有较高杂质的第二p型杂质区的pn结电容器 浓度比底物。
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公开(公告)号：US08813595B2
公开(公告)日：2014-08-26
申请号：US12742824
申请日：2008-11-12
IPC分类号： F16H35/06 , F16H1/14 , G01M13/02 , F16H55/20 , F16H57/022
CPC分类号： F16H1/145 , F16H55/20 , F16H57/022 , F16H2057/0221 , G01M13/021 , Y10T74/1956
摘要： A method for adjusting the meshing position of a hypoid gear having a first gear, and a second gear meshing with the first gear and transmitting the rotary motion thereof in the direction different from the extending direction of the axis of rotation of the first gear. The method for adjusting the meshing position comprises; a) a step for displacing the second gear a plurality of times along the axial direction of rotation while meshing with the first gear, b) a step for measuring the transmission error at each displacement position and plotting the relation of the displacement distance of the second gear and the measured transmission error, c) a step for evaluating the virtual transmission error between the measured transmission errors from the measured transmission error, d) a step for subtracting the measured transmission error and the virtual transmission error from a maximum allowable transmission error to determine the difference, e) a step for determining the area of a part surrounded by the difference and the maximum allowable transmission error by integrating the difference with the displacement distance of the second gear, and f) a step for dividing the part at a predetermined area ratio and setting a point where the division line intersects the displacement distance of the second gear at the meshing position of the second gear.
摘要翻译： 一种用于调节具有第一齿轮的准双曲面齿轮的啮合位置的方法和与第一齿轮啮合的第二齿轮，并且沿与第一齿轮的旋转轴线的延伸方向不同的方向传递其旋转运动。 调整啮合位置的方法包括： a）在与所述第一齿轮啮合的同时使所述第二齿轮沿着轴向旋转多次的步骤，b）用于测量每个位移位置处的传动误差的步骤，并且绘制所述第二齿轮的位移距离的关系 齿轮和所测量的传输误差，c）根据测量的传输误差来评估所测量的传输误差之间的虚拟传输误差的步骤，d）从最大允许传输误差减去测量的传输误差和虚拟传输误差的步骤， 确定所述差异; e）通过将所述差与所述第二档位移距离进行积分来确定由所述差包围的部分的面积和所述最大允许传播误差的步骤，以及f）用于将所述部分划分为预定的步骤 并设定分割线与第二档位于距离的位移距离相交的点 第二档的铰接位置。
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公开(公告)号：US20100261720A1
公开(公告)日：2010-10-14
申请号：US12740684
申请日：2008-10-29
申请人： Takumi Sumida , Fujio Tabusa , Kazuo Sekiguchi , Takeshi Kodama , Koichi Yasumura , Yutaka Kojima , Masaaki Motoyama , Keisuke Miyajima , Kenji Yoshida , Keizo Kan , Makoto Sakamoto , Hideki Takasu , Takashi Nakagawa , Naoto Ohi , Yasuo Harada , Norikazu Hashimoto , Hironori Matsuyama , Masatoshi Iida , Shigekazu Fujita , Tae Fukushima
发明人： Takumi Sumida , Fujio Tabusa , Kazuo Sekiguchi , Takeshi Kodama , Koichi Yasumura , Yutaka Kojima , Masaaki Motoyama , Keisuke Miyajima , Kenji Yoshida , Keizo Kan , Makoto Sakamoto , Hideki Takasu , Takashi Nakagawa , Naoto Ohi , Yasuo Harada , Norikazu Hashimoto , Hironori Matsuyama , Masatoshi Iida , Shigekazu Fujita , Tae Fukushima
IPC分类号： A61K31/5377 , C07D401/14 , C07D413/14 , A61K31/497 , C07D403/14 , A61P35/00 , A61P43/00
CPC分类号： C07D401/12 , C07D403/12
摘要： The present invention provides a heterocyclic compound represented by General Formula (1): wherein R1 is a group R5—Z1—, etc., Z1 is a lower alkylene group, etc., and R5 is a group represented by General Formula; wherein R13 is a hydrogen atom, etc., m is an integer from 1 to 5; R2 is a hydrogen atom: Y is CH or N: A1 is a heterocyclic ring selected from the group consisting of indolediyl groups, wherein the heterocyclic ring may have at least one substituent: T is a group —CO—, etc.: R3 is a hydrogen atom, etc.: R4 is a lower alkyl group optionally substituted by one or more hydroxy groups, etc.: R3 and R4, together with the nitrogen atom to which they bind, may bind to each other and form a 5- to 10-membered saturated heterocyclic ring, wherein the heterocyclic ring may have at least one substituent. The heterocyclic compound of the present invention has excellent effects of suppressing the production of collagen and/or treating tumors.
摘要翻译： 本发明提供由通式（1）表示的杂环化合物：其中R1为R5-Z1-基团等，Z1为低级亚烷基等，R5为通式所示的基团。 其中R 13为氢原子等，m为1至5的整数; R2是氢原子：Y是CH或N：A1是选自吲哚二基的杂环，其中杂环可以具有至少一个取代基：T是-CO-等：R3是 氢原子等：R4是任选被一个或多个羟基取代的低级烷基等：R 3和R 4与它们所键合的氮原子一起可以彼此结合形成5- 10元饱和杂环，其中杂环可以具有至少一个取代基。 本发明的杂环化合物具有抑制胶原蛋白的生成和/或治疗肿瘤的优异效果。
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公开(公告)号：US5124770A
公开(公告)日：1992-06-23
申请号：US512501
申请日：1990-04-20
IPC分类号： H01L29/812 , H01L21/338 , H01L29/10
CPC分类号： H01L29/1075 , Y10S257/903
摘要： An FET structure with improved .alpha.-particle immunity or soft error immunity particularly provided in a semi-insulating substrate. This structure includes some layer which can prevent both electrons and holes generated in a substrate by the incidence of .alpha.-particles from being injected into the FET.
摘要翻译： 特别是在半绝缘衬底中提供了具有改进的α-粒子抗扰度或软错误抗扰性的FET结构。 该结构包括一些层，其可以通过注入到FET中的α粒子的入射来防止在衬底中产生的电子和空穴。
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公开(公告)号：US4981596A
公开(公告)日：1991-01-01
申请号：US270328
申请日：1988-11-14
申请人： Satoru Shiino , Masaki Shimotakahara , Takesi Isozaki , Masanobu Mimura , Kuniaki Takabayashi , Norikazu Hashimoto
发明人： Satoru Shiino , Masaki Shimotakahara , Takesi Isozaki , Masanobu Mimura , Kuniaki Takabayashi , Norikazu Hashimoto
CPC分类号： A61M1/3627 , A61M1/0005 , A61M1/025
摘要： A system for treating the blood of a patient, which is obtained by, for example, bleeding during an operation and thus to be autotransfused to the patient, as well as a device therefor is disclosed. The process comprises sucking the blood under a sucking pressure of 80 to 150 mmHg, filtering the sucked blood through a filter membrane of a pore size of 100 to 150 .mu.m and storing the filtered blood in a storage tank while shaking.
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公开(公告)号：US4477182A
公开(公告)日：1984-10-16
申请号：US396880
申请日：1982-07-09
CPC分类号： G03F7/70541
摘要： A pattern exposing apparatus comprising means for projecting a semiconductor device mask pattern onto the photoresist layer coated on a semiconductor substrate, and means for projecting an identification mark which is specific to each substrate onto a part of the photoresist layer.
摘要翻译： 一种图案曝光装置，包括用于将半导体器件掩模图案投影到涂覆在半导体衬底上的光刻胶层上的装置，以及用于将每个衬底特有的识别标记投影到光致抗蚀剂层的一部分上的装置。
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公开(公告)号：US4451841A
公开(公告)日：1984-05-29
申请号：US225268
申请日：1981-01-15
IPC分类号： H01L27/10 , H01L21/3213 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L23/522 , H01L27/108 , H01L27/115 , H01L29/78 , H01L27/02 , H01L29/04 , H01L29/34
CPC分类号： H01L27/10844 , H01L21/76877 , H01L21/76897 , H01L27/115
摘要： A first semiconductor circuit element including a first electrode is formed on a semiconductor substrate, an inter-layer insulating layer for insulating the first electrode is formed on the first electrode, and a first penetrating opening is provided in a part of the inter-layer insulating layer.Subsequently, a step of forming a second semiconductor circuit element is carried out, this step including a step of forming a second electrode so that at least a part thereof may overlie the inter-layer insulating layer at an area other than the first penetrating opening. Further, a subsidiary interconnection conductive layer is buried into the first opening. Another insulating layer is formed on the structure thus formed, whereupon second and third penetrating openings are respectively provided in the insulating layer over the second electrode and the interconnection subsidiary conductive layer.First and second interconnection conductors are respectively buried into the second and third penetrating openings. The first electrode is conductively connected with the second interconnection conductor in the third opening via the subsidiary interconnection conductive layer in the first opening. The second electrode is conductively connected with the first interconnection conductor in the second opening.
摘要翻译： 包括第一电极的第一半导体电路元件形成在半导体衬底上，在第一电极上形成用于绝缘第一电极的层间绝缘层，并且第一穿透开口设置在层间绝缘体的一部分中 层。 随后，执行形成第二半导体电路元件的步骤，该步骤包括形成第二电极的步骤，使得其至少一部分可以覆盖除了第一穿透开口之外的区域的层间绝缘层。 此外，辅助互连导电层被埋入第一开口中。 在由此形成的结构上形成另一绝缘层，由此在第二电极和互连副导电层上的绝缘层中分别设置第二和第三穿透开口。 第一和第二互连导体分别埋入第二和第三穿透开口中。 第一电极通过第一开口中的辅助互连导电层与第三开口中的第二互连导体导电连接。 第二电极与第二开口中的第一互连导体导电连接。
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10.发明授权Method for controlling the degree of side-etch in thin oxide films by photo-etching process 失效用于通过光蚀刻工艺控制薄氧化膜中的侧蚀刻程度的方法
公开(公告)号：US3942982A
公开(公告)日：1976-03-09
申请号：US467606
申请日：1974-05-06
IPC分类号： H05K3/06 , G03F7/085 , G03F7/11 , H01L21/027 , H01L21/30 , H01L21/306 , H01L21/311 , G03C5/00 , B60B9/00
CPC分类号： G03F7/11 , G03F7/085 , H01L21/31111
摘要： In selectively etching a solid oxide thin film which has chemisorbed water (surface hydroxyl groups) in its surface, the thin film is surface-treated with an organic compound which has within its molecule a functional group to react with the surface hydroxyl groups. Thereafter, photo-etching is performed by the conventional method by applying a thin film of a photosensitive organic polymer onto the treated thin film. Through selection of the sort of the organic compound, the degree of side-etch arising in the process of the selective etch can be controlled.
摘要翻译： 在选择性蚀刻其表面具有化学吸附水（表面羟基）的固体氧化物薄膜时，薄膜用分子内具有与表面羟基反应的官能团的有机化合物进行表面处理。 此后，通过将常规方法通过将光敏有机聚合物的薄膜施加到经处理的薄膜上进行光蚀刻。 通过选择这种有机化合物，可以控制在选择性蚀刻过程中产生的侧蚀刻程度。
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