公开(公告)号：US4377819A

公开(公告)日：1983-03-22

申请号：US032017

申请日：1979-04-20

申请人： Yoshio Sakai ,  Toshiaki Masuhara ,  Osamu Minato ,  Toshio Sasaki ,  Hisao Katto ,  Norikazu Hashimoto ,  Shin-ichi Muramatsu ,  Akihiro Tomozawa

发明人： Yoshio Sakai ,  Toshiaki Masuhara ,  Osamu Minato ,  Toshio Sasaki ,  Hisao Katto ,  Norikazu Hashimoto ,  Shin-ichi Muramatsu ,  Akihiro Tomozawa

IPC分类号： G11C11/412 ,  H01L21/02 ,  H01L21/318 ,  H01L21/822 ,  H01L27/04 ,  H01L27/06 ,  H01L27/11 ,  H01L29/06 ,  H01L29/40 ,  H01L29/41 ,  H01L29/04

CPC分类号： H01L29/402 ,  H01L21/3185 ,  H01L27/0605 ,  H01L27/1112 ,  H01L28/20 ,  H01L29/41

摘要： A semiconductor device including at least a resistance element formed of polycrystalline silicon having a high resistivity. An electrode is provided on the high resistance polycrystalline silicon region with a silicon dioxide film and a silicon nitride film being interposed therebetween. The electrode is coupled to the ground potential. In this manner, high stability is obtained in the behavior of the resistance element inasmuch as the formation of a parasitic MOS device under said high resistance region is suppressed, and the threshold voltage of any such MOS device is made raised.

摘要翻译： 一种半导体器件，至少包括由具有高电阻率的多晶硅形成的电阻元件。 在具有二氧化硅膜的高电阻多晶硅区域上设置电极，并且在其间插入有氮化硅膜。 电极与地电位耦合。 以这种方式，由于抑制了在所述高电阻区域下的寄生MOS器件的形成，所以电阻元件的性能得到了很高的稳定性，并且提高了任何这种MOS器件的阈值电压。

公开(公告)号：US4609835A

公开(公告)日：1986-09-02

申请号：US471130

申请日：1983-03-01

申请人： Yoshio Sakai ,  Toshiaki Masuhara ,  Osamu Minato ,  Toshio Sasaki

发明人： Yoshio Sakai ,  Toshiaki Masuhara ,  Osamu Minato ,  Toshio Sasaki

IPC分类号： G11C11/412 ,  H01L27/06 ,  H01L27/085 ,  H01L27/11 ,  G11C11/40 ,  H01L27/04 ,  H01L29/78 ,  H03K19/094

CPC分类号： H01L27/0688 ,  G11C11/412 ,  H01L27/085 ,  H01L27/1104 ,  H01L27/1112

摘要： Disclosed is a semiconductor integrated circuit which comprises an n-type silicon substrate, a p-type well region having an opening at a part thereof, which is formed on the surface portion of the substrate, an MOS transistor formed in the p-type region and a resistance layer extended from the drain region of the MOS transistor to the opening of the p-type well region through a insulating film formed on the surface of the substrate, in which the drain region of the MOS transistor is electrically connected to the silicon substrate through the resistance layer so that a current is supplied to the MOS transistor.

摘要翻译： 公开了一种半导体集成电路，其包括n型硅衬底，形成在衬底的表面部分上的具有开口的p型阱区，形成在p型区域中的MOS晶体管 以及电阻层，其通过形成在所述衬底的表面上的绝缘膜从所述MOS晶体管的漏极区延伸到所述p型阱区的开口，其中所述MOS晶体管的漏极区域与所述硅 衬底通过电阻层，以便向MOS晶体管提供电流。

公开(公告)号：US4261004A

公开(公告)日：1981-04-07

申请号：US929959

申请日：1978-08-01

申请人： Toshiaki Masuhara ,  Osamu Minato ,  Yoshio Sakai ,  Toshio Sasaki ,  Masaharu Kubo ,  Kotaro Nishimura ,  Tokumasa Yasui

发明人： Toshiaki Masuhara ,  Osamu Minato ,  Yoshio Sakai ,  Toshio Sasaki ,  Masaharu Kubo ,  Kotaro Nishimura ,  Tokumasa Yasui

IPC分类号： H03F1/52 ,  H01L21/02 ,  H01L21/822 ,  H01L23/62 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L29/78 ,  H03F1/42

CPC分类号： H01L28/20 ,  H01L27/0251 ,  H01L27/0288

摘要： On the surface of an insulating film formed on the surface of a semiconductor substrate on which an MOS type semiconductor device to be protected is formed, there are formed a first polycrystal silicon member having input and output terminals and a resistivity lower than 1 K.OMEGA./.quadrature. and a second polycrystalline silicon member having a resistivity lower than 1 K.OMEGA./.quadrature. and being maintained at a fixed potential. This second polycrystalline silicon member faces at least a part of the first silicon member with polycrystalline silicon of a resistivity higher than 100 K.OMEGA./.quadrature. interposed therebetween. The input terminal of the first polycrystalline silicon member is connected to an input pad of the MOS type semiconductor device to be protected and the output terminal of the first polycrystalline silicon member is connected to an input gate of the semiconductor device to be protected. The input gate of the semiconductor device is protected by utilizing the punch-through effect in the interior of the polycrystalline silicon having a resistivity higher than 100 K.OMEGA./.quadrature..

摘要翻译： 在形成有要形成有待保护的MOS型半导体器件的半导体衬底的表面上的绝缘膜的表面上形成有具有输入和输出端子的电阻率低于1KΩ的第一多晶硅元件， 并且具有电阻率低于1KΩ/□并且保持在固定电位的第二多晶硅部件。 该第二多晶硅部件面对第一硅部件的至少一部分，其中多晶硅的电阻率高于100KΩ，并插入其间。 第一多晶硅部件的输入端子连接到要被保护的MOS型半导体器件的输入焊盘，并且第一多晶硅部件的输出端子连接到待保护的半导体器件的输入栅极。 半导体器件的输入栅极通过利用电阻率高于100KΩ/□的多晶硅的内部的穿透效应来保护。

公开(公告)号：US4797717A

公开(公告)日：1989-01-10

申请号：US039291

申请日：1987-04-17

申请人： Koichiro Ishibashi ,  Osamu Minato ,  Toshiaki Masuhara ,  Yoshio Sakai ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Shoji Hanamura ,  Nobuyuki Moriwaki ,  Shigeru Honjyo ,  Kiyotsugu Ueda

发明人： Koichiro Ishibashi ,  Osamu Minato ,  Toshiaki Masuhara ,  Yoshio Sakai ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Shoji Hanamura ,  Nobuyuki Moriwaki ,  Shigeru Honjyo ,  Kiyotsugu Ueda

IPC分类号： G11C11/403 ,  H01L21/8234 ,  H01L21/8244 ,  H01L27/088 ,  H01L27/10 ,  H01L27/11 ,  H01L29/45 ,  H01L29/78 ,  H01L27/02 ,  H01L29/04

CPC分类号： H01L29/456 ,  H01L27/1112 ,  Y10S257/904

摘要： Each of the memory cells in a SRAM includes two driver MOS transistors, two transfer gate MOS transistors and two load resistances. The gate electrode layers of the MOS transistors are formed from a first-level conductive layer provided on the surface of a semiconductor substrate. The source regions of the two driver MOS transistors in each memory cell are connected in common and further connected to a ground potential point through a second-level conductive layer. The two load resistances in each memory cell are formed from a third-level high-resistance material layer. The second-level conductive layer is formed from a low-resistance material layer. Thus the resistance of the sources of the two driver MOS transistors is lowered.

摘要翻译： SRAM中的每个存储单元包括两个驱动器MOS晶体管，两个传输门MOS晶体管和两个负载电阻。 MOS晶体管的栅极电极层由设置在半导体衬底的表面上的第一级导电层形成。 每个存储单元中的两个驱动器MOS晶体管的源极区域共同连接，并且通过第二级导电层进一步连接到地电位点。 每个存储单元中的两个负载电阻由第三级高电阻材料层形成。 第二级导电层由低电阻材料层形成。 因此，两个驱动器MOS晶体管的源极的电阻降低。

公开(公告)号：US4792841A

公开(公告)日：1988-12-20

申请号：US634037

申请日：1984-07-24

申请人： Kouichi Nagasawa ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Satoshi Meguro

发明人： Kouichi Nagasawa ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Satoshi Meguro

IPC分类号： H01L29/78 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8244 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11 ,  H01L29/04

CPC分类号： H01L27/1112 ,  H01L21/28525 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/522 ,  H01L23/53271 ,  H01L2924/0002 ,  Y10S257/903

摘要： Disclosed is an MOSIC including a plurality of silicon gate type MOSFET's in which, after the polycrystalline silicon wirings are formed simultaneously with polycrystalline silicon gates, electrodes contacted with the source and drain regions are made of polycrystalline silicon so as to be connected to the polycrystalline silicon wirings, thereby to prevent the shallow pn junctions of the source and drain regions from being destroyed by the contacts and to provide a high degree of integration to one silicon chip.

摘要翻译： 公开了包括多个硅栅型MOSFET的MOSIC，其中在与多晶硅栅极同时形成多晶硅布线之后，与源极和漏极区域接触的电极由多晶硅制成，以便连接到多晶硅 从而防止源极和漏极区域的浅的pn结被触点破坏并提供与一个硅芯片的高度集成。

公开(公告)号：US5237528A

公开(公告)日：1993-08-17

申请号：US822325

申请日：1992-01-17

申请人： Hideo Sunami ,  Tokuo Kure ,  Masanobu Miyao ,  Yoshifumi Kawamoto ,  Katsuhiro Shimohigashi ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Mitsumasa Koyanagi ,  Shinji Shimizu

发明人： Hideo Sunami ,  Tokuo Kure ,  Masanobu Miyao ,  Yoshifumi Kawamoto ,  Katsuhiro Shimohigashi ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Mitsumasa Koyanagi ,  Shinji Shimizu

IPC分类号： G11C11/404 ,  H01L27/108 ,  H01L29/94

CPC分类号： G11C11/404 ,  H01L27/10829 ,  H01L27/10841 ,  H01L29/945

摘要： A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.

摘要翻译： 半导体存储器包括具有数据存储部分的电容器和绝缘栅场效应晶体管。 该电容器由在半导体衬底中形成的沟槽的侧壁和底部以及形成在侧壁和基底上的电容器电极在绝缘膜上形成并且电连接 到绝缘栅场效应晶体管的源极或漏极。 提供了各种实施例，用于减小尺寸并防止其它存储单元之间的泄漏，包括形成叠层电容器，在电容器上形成晶体管，使用用于晶体管的绝缘体上硅布置，形成公共电容器板并提供高杂质层 底物。

公开(公告)号：US5214496A

公开(公告)日：1993-05-25

申请号：US452683

申请日：1989-12-19

申请人： Hideo Sunami ,  Tokuo Kure ,  Masanobu Miyao ,  Yoshifumi Kawamoto ,  Katsuhiro Shimohigashi ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Mitsumasa Koyanagi ,  Shinji Shimizu

发明人： Hideo Sunami ,  Tokuo Kure ,  Masanobu Miyao ,  Yoshifumi Kawamoto ,  Katsuhiro Shimohigashi ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Mitsumasa Koyanagi ,  Shinji Shimizu

IPC分类号： G11C11/404 ,  H01L27/108 ,  H01L29/94

CPC分类号： H01L27/10829 ,  G11C11/404 ,  H01L27/10841 ,  H01L29/945

摘要： A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.

公开(公告)号：US5132771A

公开(公告)日：1992-07-21

申请号：US503928

申请日：1990-04-04

申请人： Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Akihiro Shimizu ,  Koichiro Ishibashi ,  Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Eiji Takeda ,  Yoshio Sakai ,  Takashi Nishida ,  Osamu Minato ,  Toshiaki Masuhara ,  Shoji Hanamura ,  Shigeru Honjo ,  Nobuyuki Moriwaki

发明人： Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Akihiro Shimizu ,  Koichiro Ishibashi ,  Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Eiji Takeda ,  Yoshio Sakai ,  Takashi Nishida ,  Osamu Minato ,  Toshiaki Masuhara ,  Shoji Hanamura ,  Shigeru Honjo ,  Nobuyuki Moriwaki

IPC分类号： G11C11/412 ,  H01L27/11

CPC分类号： G11C11/4125 ,  H01L27/1104 ,  Y10S257/903

摘要： A semiconductor static random access memory having a high .alpha.-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor. The gate electrode of one of the two first insulated gate field effect transistors and the drain region of the other insulated gate field effect transistor, on one hand, and the drain region of the one insulated gate field effect transistor and the gate electrode of the other insulated gate field effect transistor, on the other hand, are electrically cross-coupled mutually through first and second electrically conductive films, respectively. Also, to increase packing density and enhance immunity to soft error, the gate electrodes of the first and second insulated gate field effect transistors extend substantially in parallel with one another and the channel regions of the first and second insulated gate field effect transistors extend substantially in parallel with one another.

摘要翻译： 提供了具有高α射线抗扰度和高封装密度的半导体静态随机存取存储器，其也能够进行高速操作。 半导体存储器件包括每个包括触发器电路的静态随机存取存储器单元。 每个触发器电路的存储节点分别形成在夹在第一绝缘栅场效应晶体管的栅电极和第二绝缘栅场效应晶体管的栅电极之间的区域处的各pn结。 pn结的面积小于第一或第二绝缘栅场效应晶体管的沟道部分的面积。 两个第一绝缘栅场效应晶体管中的一个的栅极电极和另一个绝缘栅场效应晶体管的漏极区域以及一个绝缘栅场效应晶体管的漏极区域和另一个绝缘栅极场效应晶体管的栅极电极 另一方面，绝缘栅场效应晶体管分别通过第一和第二导电膜互相交叉耦合。 此外，为了增加封装密度并增强对软误差的抵抗力，第一和第二绝缘栅场效应晶体管的栅极彼此基本平行地延伸，并且第一和第二绝缘栅场效应晶体管的沟道区域基本上以 彼此平行。

公开(公告)号：US5028975A

公开(公告)日：1991-07-02

申请号：US527641

申请日：1990-05-23

申请人： Kouichi Nagasawa ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Satoshi Meguro

发明人： Kouichi Nagasawa ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Satoshi Meguro

IPC分类号： H01L29/78 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8244 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11

CPC分类号： H01L27/1112 ,  H01L21/28525 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/522 ,  H01L23/53271 ,  H01L2924/0002 ,  Y10S257/903

摘要： Disclosed is an MOSIC including a plurality of silicon gate type MOSFET's in which, after polycrystalline silicon wirings are formed simultaneously with polycrystalline silicon gates, the electrodes contacted with the source and drain regions are made of polycrystalline silicon so as to be connected to the polycrystalline silicon wirings, thereby to prevent the shallow pn junctions of the source and drain regions from being destroyed by the contacts and to provide a high degree of integration to one silicon chip.

公开(公告)号：US4901128A

公开(公告)日：1990-02-13

申请号：US934556

申请日：1986-11-24

申请人： Hideo Sunami ,  Tokuo Kure ,  Masanobu Miyao ,  Yoshifumi Kawamoto ,  Katsuhiro Shimohigashi ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Mitsumasa Koyanagi ,  Shinji Shimizu

发明人： Hideo Sunami ,  Tokuo Kure ,  Masanobu Miyao ,  Yoshifumi Kawamoto ,  Katsuhiro Shimohigashi ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Mitsumasa Koyanagi ,  Shinji Shimizu

IPC分类号： G11C11/404 ,  H01L27/108 ,  H01L29/94

CPC分类号： G11C11/404 ,  H01L27/10829 ,  H01L27/10841 ,  H01L29/945

摘要： A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.

摘要翻译： 半导体存储器包括具有数据存储部分的电容器和绝缘栅场效应晶体管。 该电容器由在半导体衬底中形成的沟槽的侧壁和底部以及形成在侧壁和基底上的电容器电极在绝缘膜上形成并且电连接 到绝缘栅场效应晶体管的源极或漏极。 提供了各种实施例，用于减小尺寸并防止其它存储单元之间的泄漏，包括形成叠层电容器，在电容器上形成晶体管，使用用于晶体管的绝缘体上硅布置，形成公共电容器板并提供高杂质层 底物。