公开(公告)号：US09287887B2

公开(公告)日：2016-03-15

申请号：US14309325

申请日：2014-06-19

Applicant: PANASONIC CORPORATION

Inventor： Koji Obata ,  Kazuo Matsukawa ,  Yosuke Mitani

IPC: H03M1/06 ,  H03M1/66 ,  H04L5/14 ,  H03M1/74 ,  H03M3/00

CPC classification number: H03M1/0614 ,  H03M1/0665 ,  H03M1/66 ,  H03M1/74 ,  H03M3/368 ,  H03M3/464 ,  H03M3/50 ,  H04L5/1461

Abstract: DEM circuit (130) includes a switch (131) configured to receive an N-bit digital input signal (SD1) and shift bit positions of the digital input signal (SD1) based on a switch control signal (SC) in a circulating pattern to output the digital input signal (SD1) as an N-bit digital output signal (SD2), where N is an integer greater than or equal to 2, and a switch control signal generation circuit (132) including a plurality of pointers which move in an identical direction based on a predetermined rule, and configured to generate the switch control signal (SC), each time when the digital input signal (SD1) is input to the switch (131), by using the pointers in a predetermined order.

Abstract translation: DEM电路（130）包括：开关（131），被配置为基于循环模式的开关控制信号（SC），以循环模式接收N位数字输入信号（SD1）和数字输入信号（SD1）的位位置 输出数字输入信号（SD1）作为N位数字输出信号（SD2），其中N是大于或等于2的整数;以及开关控制信号产生电路（132），包括多个指针 基于预定规则的相同方向，并且被配置为在每当数字输入信号（SD1）被输入到开关（131）时，通过以预定顺序使用指针来产生开关控制信号（SC）。

公开(公告)号：US09025309B2

公开(公告)日：2015-05-05

申请号：US13800800

申请日：2013-03-13

Applicant: Panasonic Corporation

Inventor： Kazuo Matsukawa ,  Shiro Sakiyama ,  Naoshi Yanagisawa

IPC: H01G4/005 ,  H01G4/38 ,  H01L23/522 ,  H01L27/08

CPC classification number: H01G4/385 ,  H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor array includes a plurality of comb capacitors sharing a common comb electrode. At least one of the comb capacitors has a comb electrode as a single base part. Each of the other ones of the comb capacitors has an electrode formed by coupling a plurality of base parts. In the other ones of the comb capacitors, a space between a wire coupling the base parts and an end of each of comb teeth of the common electrode, which is interposed between the base parts, is larger than a space between a base of each of the base parts of the plurality of comb capacitors and an end of each of the comb teeth of the common electrode, which is interposed between comb teeth of the base part.

Abstract translation: 电容器阵列包括共享共同梳电极的多个梳状电容器。 梳状电容器中的至少一个具有梳状电极作为单个基底部分。 梳状电容器中的每一个具有通过耦合多个基部而形成的电极。 在梳状电容器的另一个中，连接基部的电线与公共电极的每个梳齿之间的间隔在基座之间的空间大于基座之间的空间 多个梳状电容器的基部和公共电极的每个梳齿的端部插入在基部的梳齿之间。

公开(公告)号：US08981978B2

公开(公告)日：2015-03-17

申请号：US14072743

申请日：2013-11-05

Applicant: Panasonic Corporation

Inventor： Shiro Dosho ,  Kazuo Matsukawa ,  Yosuke Mitani

IPC: H03M3/00 ,  H03H11/12

CPC classification number: H03M3/454 ,  H03H11/1252 ,  H03M3/404 ,  H03M3/438

Abstract: Two resistive elements and a capacitive element are coupled between a first node and each of an inverting input terminal of an operational amplifier, an output terminal of the operational amplifier, and a common node. A resistive element and a capacitive element are coupled between the first node and a signal input terminal. Two capacitive elements and a resistive element are coupled between a second node and each of the inverting input terminal, the output terminal, and the common node. Two capacitive elements are coupled between the second node and each of the signal input terminal, and the common node.

Abstract translation: 两个电阻元件和电容元件耦合在运算放大器的第一节点和反相输入端子，运算放大器的输出端子和公共节点之间。 电阻元件和电容元件耦合在第一节点和信号输入端子之间。 两个电容元件和电阻元件耦合在第二节点和反相输入端子，输出端子和公共节点之间。 两个电容元件耦合在第二节点和每个信号输入端和公共节点之间。

公开(公告)号：US08937567B2

公开(公告)日：2015-01-20

申请号：US13779366

申请日：2013-02-27

Applicant: Panasonic Corporation

Inventor： Koji Obata ,  Kazuo Matsukawa ,  Yosuke Mitani ,  Shiro Dosho

IPC: H03M3/00 ,  H03F3/45

CPC classification number: H03M3/50 ,  H03F3/45076 ,  H03M3/438

Abstract: A delta-sigma modulator includes: an integrator having an operational amplifier; a quantizer quantizing an output of the integrator; a first D-A converter converting an output of the quantizer to a current signal to provide negative feedback to the operational amplifier; a feedforward path feeding forward an input of the integrator to the quantizer; and a second D-A converter converting the output of the quantizer to a current signal to provide negative feedback to the quantizer. The integrator includes a resistive element having a first end connected to the input of the integrator and a second end connected to an inverting input of the operational amplifier, n capacitive circuits connected in series between the inverting input and an output of the operational amplifier, and (n−1) resistive elements each having a first end connected to an interconnecting node of the capacitive circuits and a second end connected to a common node.

Abstract translation: Δ-Σ调制器包括：具有运算放大器的积分器; 量化器，对积分器的输出进行量化; 将量化器的输出转换为电流信号的第一D-A转换器，以向运算放大器提供负反馈; 前馈路径将积分器的输入馈送到量化器; 以及将量化器的输出转换为电流信号的第二D-A转换器，以向量化器提供负反馈。 积分器包括电阻元件，其电阻元件的第一端连接到积分器的输入端，第二端连接到运算放大器的反相输入端，n个电容电路串联连接在反相输入端和运算放大器的输出端之间，以及 （n-1）个电阻元件，每个电阻元件的第一端连接到电容电路的互连节点，第二端连接到公共节点。

公开(公告)号：US09077358B2

公开(公告)日：2015-07-07

申请号：US14300657

申请日：2014-06-10

Applicant: PANASONIC CORPORATION

Inventor： Takuji Miki ,  Kazuo Matsukawa ,  Takashi Morie ,  Shiro Sakiyama

IPC: H03M1/12 ,  H03M1/08 ,  H03M1/06 ,  H03M1/80 ,  H03M1/00 ,  H03M3/00 ,  H03M1/46

CPC classification number: H03M1/08 ,  H03M1/00 ,  H03M1/0641 ,  H03M1/12 ,  H03M1/466 ,  H03M1/468 ,  H03M1/804 ,  H03M3/30

Abstract: In a successive approximation AD converter, a noise generator outputs the output of a ΔΣ modulator as a noise signal. A selector circuit can output the noise signal, in place of a digital signal for generating a comparison-target voltage for the next bit, to a capacitor element of a capacitance DAC. During sampling of an analog input voltage, the noise signal is supplied to the capacitance DAC via the selector circuit, and thereafter normal successive approximation operation is executed.

Abstract translation: 在逐次逼近AD转换器中，噪声发生器输出＆Dgr＆amp; 调制器作为噪声信号。 选择器电路可以代替用于产生下一位的比较目标电压的数字信号，将噪声信号输出到电容DAC的电容器元件。 在采样模拟输入电压时，噪声信号通过选择电路提供给电容DAC，之后执行正常的逐次逼近操作。

公开(公告)号：US08963753B2

公开(公告)日：2015-02-24

申请号：US13898420

申请日：2013-05-20

Applicant: Panasonic Corporation

Inventor： Shiro Dosho ,  Kazuo Matsukawa ,  Masao Takayama ,  Yosuke Mitani

IPC: H03M3/00 ,  H03M1/12

CPC classification number: H03M1/12 ,  H03M3/344 ,  H03M3/43 ,  H03M3/454

Abstract: An oversampling A/D converter includes a first filter including a first resistive element, a first capacitive element, a second resistive element, an operational amplifier, and a second capacitive element; a second filter receiving an output of the first filter; a third filter including a third resistive element, a third capacitive element, and a fourth resistive element; a quantizer receiving an output of the third filter and generating a digital signal; and a D/A converter converting the digital signal to an analog current signal. The D/A converter inputs the generated analog current signal to an inverting input terminal of the operational amplifier.

Abstract translation: 过采样A / D转换器包括：第一滤波器，包括第一电阻元件，第一电容元件，第二电阻元件，运算放大器和第二电容元件; 接收第一滤波器的输出的第二滤波器; 第三滤波器，包括第三电阻元件，第三电容元件和第四电阻元件; 量化器，接收第三滤波器的输出并产生数字信号; 以及将数字信号转换成模拟电流信号的D / A转换器。 D / A转换器将产生的模拟电流信号输入到运算放大器的反相输入端。

公开(公告)号：US08872684B2

公开(公告)日：2014-10-28

申请号：US14292084

申请日：2014-05-30

Applicant: Panasonic Corporation

Inventor： Kazuo Matsukawa ,  Yosuke Mitani ,  Koji Obata

IPC: H03M3/00 ,  H03H7/01 ,  H03M1/00 ,  H03M1/12

CPC classification number: H03M3/30 ,  H03H7/0138 ,  H03H11/0433 ,  H03H11/126 ,  H03H11/1291 ,  H03H11/32 ,  H03M1/00 ,  H03M1/12 ,  H03M1/406 ,  H03M3/396

Abstract: A delta-sigma A/D converter includes a loop filter including a resonant filter, a quantizer, and a feedback D/A converter. The resonant filter includes a resonator including a resistor and a capacitor, and a feedback path through which an output of the resonator is positively fed back to an input of the resonator. The resonant filter operates as an oscillator or a filter under the on/off control of a first switch. At least one of the resistor and the capacitor of the resonator is configured to allow a resistance value or a capacitance value thereof to be adjusted based on a third external signal.

Abstract translation: Δ-ΣA / D转换器包括一个包括谐振滤波器，量化器和反馈D / A转换器的环路滤波器。 谐振滤波器包括包括电阻器和电容器的谐振器，以及谐振器的输出被积极反馈到谐振器的输入端的反馈路径。 谐振滤波器在第一开关的开/关控制下用作振荡器或滤波器。 谐振器的电阻器和电容器中的至少一个被配置为允许基于第三外部信号来调整电阻值或其电容值。

公开(公告)号：US09178530B2

公开(公告)日：2015-11-03

申请号：US14139146

申请日：2013-12-23

Applicant: PANASONIC CORPORATION

Inventor： Yosuke Mitani ,  Kazuo Matsukawa ,  Koji Obata ,  Shiro Dosho

IPC: H04B1/48 ,  H03M3/00 ,  H04B1/44

CPC classification number: H03M3/422 ,  H03M3/44 ,  H03M3/454 ,  H04B1/44

Abstract: A delta sigma modulator includes a filter circuit including an integrator having an operational amplifier; a first addition circuit provided between an output section of the filter circuit and an input section of a quantizer, and including a first resistive element; and a second addition circuit including at least one of a first feedforward circuit including a second resistive element or a first feedback circuit configured to feed back, as an analog signal, a digital output signal having been quantized by the quantizer, to an input section of the quantizer, wherein at least one of the first addition circuit or the first feedback circuit includes a phase compensator.

Abstract translation: ΔΣ调制器包括具有运算放大器的积分器的滤波电路; 第一加法电路，设置在滤波器电路的输出部分和量化器的输入部分之间，并包括第一电阻元件; 以及第二加法电路，其包括包括第二电阻元件或第一反馈电路的第一前馈电路中的至少一个，所述第一反馈电路被配置为将由量化器量化的数字输出信号作为模拟信号反馈到 所述量化器，其中所述第一加法电路或所述第一反馈电路中的至少一个包括相位补偿器。

公开(公告)号：US20130249718A1

公开(公告)日：2013-09-26

申请号：US13898420

申请日：2013-05-20

Applicant: PANASONIC CORPORATION

Inventor： Shiro Dosho ,  Kazuo Matsukawa ,  Masao Takayama ,  Yosuke Mitani

IPC: H03M1/12

CPC classification number: H03M1/12 ,  H03M3/344 ,  H03M3/43 ,  H03M3/454

Abstract: An oversampling A/D converter includes a first filter including a first resistive element, a first capacitive element, a second resistive element, an operational amplifier, and a second capacitive element; a second filter receiving an output of the first filter; a third filter including a third resistive element, a third capacitive element, and a fourth resistive element; a quantizer receiving an output of the third filter and generating a digital signal; and a D/A converter converting the digital signal to an analog current signal. The D/A converter inputs the generated analog current signal to an inverting input terminal of the operational amplifier.

Abstract translation: 过采样A / D转换器包括：第一滤波器，包括第一电阻元件，第一电容元件，第二电阻元件，运算放大器和第二电容元件; 接收第一滤波器的输出的第二滤波器; 第三滤波器，包括第三电阻元件，第三电容元件和第四电阻元件; 量化器，接收第三滤波器的输出并产生数字信号; 以及将数字信号转换成模拟电流信号的D / A转换器。 D / A转换器将产生的模拟电流信号输入到运算放大器的反相输入端。